Claims
- 1. A method of manufacturing a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon, comprising;forming a metal etch barrier layer forming a first gate electrode of a first metal gate electrode material having a work function compatible with the first transistor over the metal etch barrier layer; and forming a second gate electrode of a second metal gate electrode material having a work function compatible with the second transistor over the metal etch barrier layer.
- 2. The method as recited in claim 1 wherein forming a first metal gate electrode material includes forming a metal gate electrode.
- 3. The method as recited in claim 1 wherein forming a second metal gate electrode material includes forming a metal gate electrode.
- 4. The method as recited in claim 1 wherein forming a first gate electrode includes forming a gate electrode including a doped polysilicon doped with an n-type dopant.
- 5. The method as recited in claim 1 forming a second gate electrode includes forming a gate electrode including a metal silicide.
- 6. The method as recited in claim 5 wherein forming a gate electrode including metal silicide includes forming a gate electrode including tungsten silicide.
- 7. The method as recited in claim 1, wherein forming a metal etch barrier layer includes forming a metal etch barrier layer having a high dielectric constant.
- 8. The method as recited in claim 7 wherein forming a metal etch barrier layer includes forming a metal etch barrier layer including tantalum pentoxide, silicon nitride or aluminum oxide.
- 9. The method as recited in claim 1 further including forming a gate dielectric prior to forming the first and second gate electrodes.
- 10. The method as recited in claim 9 wherein forming a gate dielectric includes forming a gate silicon dioxide to a thickness of about 2 nm or less.
- 11. The method as recited in claim 1 wherein forming a first metal gate electrode material includes forming a metal gate electrode material including tantalum, tungsten, titanium, titanium nitride, or tantalum nitride.
- 12. The method as recited in claim 1 wherein forming the first gate electrode includes forming a portion of an NMOS device and forming the second gate electrode includes forming a portion of a PMOS device.
- 13. The method as recited in claim 1 wherein forming the first gate electrode includes forming a portion of a PMOS device and forming the second gate electrode includes forming a portion of an NMOS device.
- 14. The method as recited in claim 1 wherein forming a first gate electrode includes forming a gate electrode with a material having a work function of about 4.2 eV and forming a second gate electrode includes forming a gate electrode with a material having a work function of about 5.2 eV.
CROSS-REFERENCE TO PROVISIONAL APPLICATION
This application claims the benefit of U.S. Provisional Application No. 60/168,911 entitled “CMOS WITH METAL GATES BY WORK FUNCTION ENGINEERING,” to Isik Kizilyalli, et. al., filed on Dec. 3, 1999, which is commonly assigned with the present invention and incorporated herein by reference as if reproduced herein in its entirety.
US Referenced Citations (8)
Foreign Referenced Citations (4)
Number |
Date |
Country |
0 915 510 |
May 1999 |
EP |
1 005 094 |
May 2000 |
EP |
1 032 033 |
Aug 2000 |
EP |
2 347 789 |
Sep 2000 |
GB |
Non-Patent Literature Citations (2)
Entry |
M. Buchanan; “Scaling the Gate Dielectric: Materials, Integration and Reliability”; Journal of Resarch & Development, vol. 43,No. 3 IBM 1999; pp. 1-20. |
B. Maiti and P.J. Tobin; “Metal Gates for Advanced CMOS Technology”; Part of the SPIE Conference on Microelectronic Device Technology III, Santa Clara, California 1999, SPIE vol. 3881; pp. 46-57. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/168911 |
Dec 1999 |
US |