Semiconductor device having a trench gate and method of fabricating the same

Abstract

A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIGS. 1 to 8 show cross sections of an exemplary process flow of manufacturing a semiconductor device having a trench gate; and

FIGS. 9 to 16 are cross sections of another exemplary process flow of manufacturing a semiconductor device having a trench gate.

Claims

1. A method of fabricating a semiconductor device having a trench gate, comprising: providing a semiconductor substrate having a trench etch mask thereon;etching the semiconductor substrate to form a trench having a sidewall and a bottom using the trench etch mask as a shield;doping impurities into the semiconductor substrate through the trench to form a doped region;etching the semiconductor substrate underlying the trench to form an extended portion;forming a gate insulating layer on the trench and the extended portion; andforming a trench gate in the trench and the extended portion.

2. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, wherein forming the trench etch mask further comprises: forming a silicon nitride layer on the semiconductor substrate;forming a photoresist pattern having an opening on the silicon nitride layer by photolithography;etching the silicon nitride layer through the opening using the photoresist pattern as a mask to form the trench etch mask; andremoving the photoresist pattern.

3. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, wherein the doped region is formed by doping impurities using gas phase doping (GPD) or liquid phase doping (LPD).

4. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, wherein the impurities comprise As, P, B, or Sb.

5. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, further comprising forming a dielectric liner on the sidewall of the trench before forming the extended portion.

6. The method of fabricating a semiconductor device having a trench gate as claimed in claim 5, further comprising removing the dielectric liner before forming the gate insulating layer.

7. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, wherein the gate insulating layer is formed by thermal oxidation or chemical vapor deposition.

8. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, wherein the extended portion is cylinder-shaped or bowl-shaped.

9. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, further comprising: forming a sacrificial oxide layer on a surface of the extended portion by thermal oxidation before forming the extended portion; andremoving the sacrificial oxide layer.

10. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, wherein forming the doped region further comprising: conformally forming a doped insulating layer on the sidewall and the bottom of the trench removing the doped insulating layer at the bottom of the trench to leave a doped insulating spacer;forming a dielectric liner on the doped insulating spacer; anddriving dopants of the doped insulating spacer into the semiconductor substrate adjacent to the doped insulating spacer by thermal oxidation.

11. The method of fabricating a semiconductor device having a trench gate as claimed in claim 10, further comprising removing the dielectric liner and the doped insulating spacer before forming the gate insulating layer.

12. The method of fabricating a semiconductor device having a trench gate as claimed in claim 10, wherein the doped insulating layer comprises phosphosilicate glass (PSG), arsenic silicate glass (ASG) or borosilicate glass (BSG).

13. The method of fabricating a semiconductor device having a trench gate as claimed in claim 11, wherein the doped insulating spacer is removed by an etching gas comprising hydrofluoric gas or an etchant comprising hydrofluoric acid.

14. The method of fabricating a semiconductor device having a trench gate as claimed in claim 10, wherein the thermal oxidation is rapid thermal oxidation and is performed at a temperature about 300° C. to 500° C.

15. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1, further comprising a doping step for a channel.

16. A semiconductor device having a trench gate, comprising: a semiconductor substrate;a trench disposed in the semiconductor substrate wherein the trench has an extended portion;a gate insulating layer formed on a sidewall of the trench and a surface of the extended portion;a doped region formed in the semiconductor substrate adjacent to the sidewall of the trench;a recessed channel in the semiconductor substrate underlying the extended portion of the trench; anda gate formed in the trench including the extended portion.

17. The semiconductor device having a trench gate as claimed in claim 16, the recessed channel has a length greater than 1.2 times the lateral dimension of the trench.

18. The semiconductor device having a trench gate as claimed in claim 16, the recessed channel has a length of about 1.5 to 3 times the lateral dimension of the trench.