Patent Application
20080029809
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-213571, filed Aug. 4, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a vertical transistor structure. More specifically, the invention relates to a vertical high-speed bipolar transistor and a vertical high-withstanding low-resistance field-effect transistor.
2. Description of the Related Art
In general, the high-speed performance factor of a bipolar transistor is expressed by cutoff frequency (fT). For high-speed and low-power consumption, high fT characteristics are required with smaller collector current (Ic). The fT characteristics of a bipolar transistor depend on the transit time of electrons (carriers) that pass a base region and a collector region and the charging/discharging time constant of each of an emitter/base junction and a collector/base junction. The transit time of electrons in the base region is a dominant factor for improving the fT characteristics. In place of conventional ion implantation, therefore, a technique of reducing the width of a base region using epitaxial growth in a base forming process has been tried.
The fT characteristics of a bipolar transistor are influenced by a shallow junction of an impurity diffusion layer serving as an emitter region, a base region and a collector region as the transistor decreases in area. Moreover, the SiGe-HBT (Heterojunction Bipolar Transistor) technique has improved the fT characteristics of the bipolar transistor. This technique employs a drift field acceleration effect in a base region, which generates a voltage gradient (electric field) in the base region by adding germanium unevenly.
However, though a further improvement of fT characteristics of a bipolar transistor requires a more reduction of base width or that of base concentration, it causes a problem of increasing base resistance (RB) and decreasing a withstanding voltage (BVceo) as tradeoff characteristics.
In a prior art horizontal high-withstanding low-resistance field-effect transistor (N-channel type in particular), the resistance of an N-type drift layer is a factor to determine the resistance of the transistor. The withstanding voltage of the transistor depends on a depletion layer extending from a P layer. In this prior art transistor, the concentration of the N-type drift layer needs to increase in order to achieve a high withstanding voltage, whereas it needs to decrease in order to achieve a low resistance.
In the horizontal high-withstanding low-resistance field effect transistor, it is effective to expand the drift layer in order to improve the performance (high withstanding voltage and low resistance). If, however, the drift layer is simply expanded, the transistor will increase in resistance.
The high-speed bipolar transistor and high-withstanding low-resistance field effect transistor have already been well known (for example, see T. Sugano (supervisor) and Y. Nagata (editor), “Very High Speed Digital Device, Series I, Very High Speed Bipolar Device,” Baifukan Co., Ltd.; G. L. Patton, J. H. comfort, B. S. Meyerson, E. Crabbe, G. Scilla, E. DeFresart, J. M. C. Stork, J. Y.-C. Sun, D. L. Harame, and J. N. Burghartz, “7G5-GHz fT SiGe-base Heterojunction Bipolar Transistors,” IEEE Electron Device Lett., Vol. 11, pp 171-173, April 1990; “Power Device Power IC Handbook,” Research Committee of High-Performance Multi-Function Power Device Power IC in the Institute of electrical Engineering of Japan, Corona Publishing Co., Ltd.; Chin-Yu Tsai, Taylor Efland, Sameer Pendharkar, Hozef Mitros, Alison Tessmer, Jeff Smith, John Erdeljac, and Lou Hutter, “16-60V Rated LDMOS Show Advanced Performance in an 0.72 μm Evolution BiCMOS Power Technology,” Mixed Signal Power Component and Power BiCMOS process Development Texas Instruments Incorporated 1997 IEEE; and V. Parthasarathy, R. Zhu, W. Peterson, M. Zunhino and R. Baird, “A 33V, 0.25 mΩ-cm2 n-channel LDMOS in a 0.65 μm Smart Power Technology for 20-30V Applications,” Transportation Silicon Technology center, Motorola SPS Proceedings of 1998 International Symposium on Power Semiconductor Device & ICs).
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate having a semiconductor layer on a major surface thereof, the semiconductor layer being formed to extend in a vertical direction of the major surface; and
a stress application layer provided on either side of the semiconductor layer, the stress application layer applying a stress to the semiconductor layer.
According to a second aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate having a semiconductor layer on a major surface thereof, the semiconductor layer being formed to extend in a vertical direction of the major surface;
a collector layer and a base layer both formed in the semiconductor layer;
a first stress application layer formed on either side of the collector layer of the semiconductor layer to apply a stress to the collector layer;
a second stress application layer formed on either side of the base layer of the semiconductor layer to apply a stress to the base layer;
a base electrode connected to the base layer;
an emitter layer provided on the semiconductor layer; and
an emitter electrode connected to the emitter layer.
According to a third aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate having a semiconductor layer on a major surface thereof, the semiconductor layer being formed to extend in a vertical direction of the major surface;
a drain layer formed in the semiconductor layer;
a stress application layer provided on either side of the drain layer of the semiconductor layer, the stress application layer applying a stress to the drain layer;
a channel region provided on the semiconductor layer;
a gate electrode provided close to the channel region;
a source layer provided in the channel region; and
a source electrode connected to the source layer.
Embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the drawings are schematic ones and the dimension ratios shown therein are different from the actual ones. The dimensions vary from drawing to drawing and so do the ratios of dimensions. The following embodiments are directed to a device and a method for embodying the technical concept of the present invention and the technical concept does not specify the material, shape, structure or configuration of components of the present invention. Various changes and modifications can be made to the technical concept without departing from the scope of the claimed invention.
A plate-shaped (or a bar-shaped) semiconductor layer (referred to as a Si post) 11a is formed on the major surface of a semiconductor substrate (e.g., Si substrate) 11 upright in the vertical direction of the substrate 11. A stress applying layer 21 is provided on either side (outer region) to apply a tensile stress (distortion stress) in the vertical direction perpendicular to the major surface of the Si substrate 11. For example, an insulating silicon nitride (SiN) film is used as the stress applying layer 21, as is a laminated film of an insulative silicon nitride film and a silicon oxide (SiO2) film, a conductive silicon germanium (SiGe) mixed-crystal film that is formed by substituting germanium for part of silicon.
Assume that in the structure shown in
A high-speed bipolar transistor and a withstanding low-resistance field-effect transistor to which the semiconductor device shown in
A plate-shaped (or bar-shaped) silicon post 11a is formed on the major surface of a silicon substrate 11. The silicon post 11a includes a collector layer (epitaxial layer) 12, a buffer layer (silicon layer) 13 and a base layer (SiGe layer) 14 in advance.
A first stress application layer 21a is formed on at least either side of the collector layer 12 to apply a tensile stress to either side of the collector layer 12 in the vertical direction. A second stress application layer 21b is formed on either side of each of the buffer layer 13 and base layer 14 to apply a tensile stress to either side of each of the layers 13 and 14 (at least the base layer 14) in the vertical direction. As the first stress application layer 21a, for example, an insulative SiN film (nitride film) or a laminated film of a SiN film and a SiO2 film is used. As the second stress application layer 21b, for example, a conductive SiGe film is used. The second stress application layer 21b applies a tensile stress to the base layer 14 and also serves as an extraction electrode for electrically connecting the base 14 to a base polysilicon electrode 15.
An insulation film 16 is provided on the major surface of the silicon substrate 11 and either side of the first stress application layer 21a. The base polysilicon electrode 15 is provided on the insulation film 16 and either side of the second stress application layer 21b.
An emitter (diffusion) layer 17 using polysilicon and an emitter polysilicon electrode 18 are provided on the surface of the silicon post 11a. Silicide layers 19a and 19b for low resistance are provided in the surface areas of the emitter polysilicon electrode 18 and base polysilicon electrode 15, respectively, when the need arises.
The emitter polysilicon electrode 18 and silicide layer 19a are insulated from the base polysilicon electrode 15, second stress application layer 21b and base layer 14 by an insulation film 20.
With the vertical high-speed bipolar transistor so configured, the carriers (electrons) injected from the emitter layer 17 can be improved in mobility in both the collector layer 12 and base layer 14, and the fT characteristics can be improved. In other words, if a tensile stress is locally applied to the silicon post 11a (the silicon post 11a is locally strained), the fT characteristics of the transistor can be improved due to an increase in carrier mobility in the base and collector layers without increasing in RB or decreasing in BVceo.
An example of a method of manufacturing the vertical high-speed bipolar transistor shown in
Referring first to
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After that, the top surface of the insulation film 16a and the insulation film 33 are removed by etching. As shown in
Referring then to
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After the resist remaining on the insulation film 20b is removed, a polysilicon film 18a serving as an emitter polysilicon electrode 18 is formed by CVD on the emitter layer 17 and insulation film 20b, as shown in
Referring then to
Finally, a laminated film of, e.g., a titanium (Ti) film and a titanium nitride (TiN) film is formed on the surface of the base polysilicon electrode 15 and that of the emitter polysilicon electrode 18 by physical vapor deposition (PVD) when the need arises. Then, the laminated film is silicified into silicide layers 19a and 19b by RTA, thereby completing a vertical high-speed bipolar transistor as shown in
As described above, a stress application layer for applying a tensile stress to either side of the plate-shaped or bar-shaped silicon post in the vertical direction of the silicon substrate, is provided on the major surface of the silicon substrate. In the vertical high-speed bipolar transistor having a collector layer, a buffer layer and a base layer in the vertical direction, an insulative stress application layer is formed on either side of the collector layer, while a conductive stress application layer is formed on either side of at least the base layer. Thus, a connecting electrode can be extracted from either side of the base layer, and a tensile stress can be locally applied to the silicon post. Therefore, the carrier mobility can be improved in the base and collector layers without increasing in RB or decreasing in BVceo, and the performance (fT characteristics) of the high-speed bipolar transistor can greatly be improved.
The vertical high-speed bipolar transistor of the second embodiment can be applied to both an NPN structure and a PNP structure. However, when it is applied to an NPN structure, the hole mobility in the collector region (P type) is improved and thus a stress application layer is provided on either side of the collector region such that a compressive stress or a tensile stress is applied to either side of the collector region in the vertical direction of the substrate.
In the third embodiment, an epitaxial substrate 41 having an N+ buried layer 40 is used in place of the silicon substrate 11. Specifically, a plate-shaped (or bar-shaped) silicon substrate 41a including an N+ buried layer 40 is formed as a semiconductor layer on the major surface of the epitaxial substrate 41. An N− drain layer (N type drift layer) 42 is formed in advance on the silicon post 41a.
A stress application layer 21 is formed on either side of at least each of the N+ buried layer 40 and the N− drain layer 42 of the silicon post 41a to apply a tensile stress to either side in the vertical direction. As the stress application layer 21, for example, an insulative SiN film (nitride film) or a laminated film of a SiN film and a SiO2 film is used.
An insulation film 43 is provided on the major surface of the epitaxial substrate 41, except where the silicon post 41a and the stress application layer 21 are formed. A gate electrode 44 is provided on the insulation film 43.
A P− channel region 45 is provided on the surface of the silicon post 41a as part of the gate electrode 44. An N+ source layer 46 is formed in part of the surface area of the P− channel region 45.
A source electrode 48 is provided on the gate electrode 44 with a gate insulation film 47 therebetween. The source electrode 48 is partly connected to the N+ source layer 46.
With the vertical high-withstanding low-resistance field-effect transistor so configured, the carriers (electrons) injected into the N− drain layer 42 can be improved in mobility in the layer 42. More specifically, the transistor can be improved in performance (increased in withstanding voltage and decreased in resistance) and its N-type drift layer (N− drain layer 42) can be decreased in resistance without lowering the withstanding voltage.
An example of a method of manufacturing the vertical high-withstanding low-resistance field-effect transistor shown in
Referring first to
After that, the resist (not shown) used for forming the silicon post 41a is eliminated and, as shown in
Referring then to
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Finally, a source electrode 48 is formed by PVD on the gate insulation film 47 and in the opening 55 to complete the vertical high-withstanding low-resistance field-effect transistor with the structure shown in
As described above, a stress application layer for applying a tensile stress to either side of the plate-shaped or bar-shaped silicon post in the vertical direction of the epitaxial substrate having an N+ buried layer, is provided on the major surface of the epitaxial substrate. In the vertical high-withstanding low-resistance field-effect transistor including an N− drain layer, a P− channel region and an N+ source layer in the vertical direction, an insulative stress application layer is formed on either side of the N− drain layer. Thus, a tensile stress can be locally applied to the drain layer. Therefore, the carrier mobility can be improved in the N− drain layer and the N-type drift layer (N− drain layer) can be decreased in resistance without lowering a withstanding voltage.
The vertical high-withstanding low-resistance field-effect transistor of the third embodiment can be applied to a P-channel type as well as an N-type. However, when it is applied to a P-channel type, the hole mobility in the P− drain layer is improved and thus a stress application layer is provided on either side of the P− drain layer such that a compressive stress or a tensile stress is applied to either side of the P− drain layer in the vertical direction of the substrate.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-213571 | Aug 2006 | JP | national |
