Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method

Abstract

A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view showing a semiconductor device according to a reference example, and FIGS. 1B and 1C are cross sectional views taken along one-dot chain lines B1-B1 and C1-C1 shown in FIG. 1A, respectively.

FIGS. 2A and 2B are graphs showing the relation between a drain current change ratio and a gate width of NMOSFET and PMOSFET, respectively, calculated for each contraction ratio of an isolation insulating film.

FIG. 3A is a plan view of a semiconductor device according to a first embodiment, and FIGS. 3B and 3C are cross sectional views taken along one-dot chain lines B3-B3 and C3-C3 shown in FIG. 3A, respectively.

FIGS. 4A and 4B are graphs showing the relation between a drain current change ratio and a thickness of an upper insulating film constituting an isolation insulating film of NMOSFET and PMOSFET, respectively, calculated for each contraction ratio of the upper insulating film.

FIGS. 5A and 5B are graphs showing the relation between a drain current change ratio and a gate width of NMOSFET and PMOSFET, respectively, calculated for each contraction ratio of an upper insulating film.

FIGS. 6A to 6C are graphs showing the relation between a drain current change ratio and a thickness of an upper insulating film constituting an isolation insulating film at 0%, 1% and 2% of the contraction ratios, calculated for each gate width.

FIGS. 7A to 7C are graphs showing the relation between a drain current change ratio and a thickness of an upper insulating film constituting an isolation insulating film at 0%, 1% and 2% of the contraction ratios of the upper insulating film, calculated for each sinking amount of the upper surface of the isolation insulating film.

FIGS. 8A to 8K are cross sectional views illustrating of a semiconductor device during manufacture in a method of manufacturing a semiconductor device according to a second embodiment.

FIGS. 9A and 9B are cross sectional views of the semiconductor device of the second embodiment.

FIGS. 10A and 10B are cross sectional views illustrating a semiconductor device during manufacture in a method of manufacturing a semiconductor device according to a third embodiment.

FIGS. 11A and 11B are cross sectional views of the semiconductor device of the third embodiment.

FIGS. 12A and 12B are cross sectional views illustrating a semiconductor device during manufacture in a method of manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 13A and 13B are cross sectional views of the semiconductor device of the fourth embodiment.

FIGS. 14A and 14B are cross sectional views illustrating a semiconductor device during manufacture in a method of manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 15A and 15B are cross sectional views of the semiconductor device of the fifth embodiment.

Claims

1. A semiconductor device comprising: a trench formed in a surface layer of a semiconductor substrate and surrounding an active region;a lower insulating film made of insulating material and filling a lower region of the trench; andan upper insulating film filling a region of the trench above the lower insulating film, the upper insulating film having therein a stress generating tensile strain in a surface layer of the active region.

2. The semiconductor device according to claim 1, wherein the lower insulating film has therein a compressive stress.

3. The semiconductor device according to claim 1, further comprising a gate electrode intersecting with the active region and having protruded portions protruding outside a border of the active region.

4. The semiconductor device according to claim 3, wherein a thickness of the upper insulating film is 50 nm or thicker under the protruded portions of the gate electrode.

5. The semiconductor device according to claim 3, wherein an upper surface of the upper insulating film in an area not covered with the gate electrode sinks from an upper surface of the active region.

6. The semiconductor device according to claim 5, wherein the upper surface of the upper insulating film in an area not covered with the gate electrode sinks from the upper surface of the active region by 50 nm or deeper.

7. The semiconductor device according to claim 1, wherein the semiconductor substrate essentially consists of silicon, and the lower insulating film and the upper insulating film essentially consist of silicon oxide.

8. A method of manufacturing a semiconductor device comprising steps of: (a) forming a trench in a surface layer of a semiconductor substrate, the trench surrounding an active region;(b) depositing a lower insulating film made of insulating material over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region;(c) depositing an upper insulating film made of insulating material having therein a tensile stress on the lower insulating film, the upper insulating film filling the empty space left in the upper space; and(d) removing the upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench.

9. The method of manufacturing the semiconductor device according to claim 8, wherein the lower insulating film and the upper insulating film essentially consists of silicon oxide, a substrate temperature during deposition at the step (c) is lower than a substrate temperature during deposition at the step (b), and the step (c) deposits the upper insulating film and thereafter executes heat treatment at a temperature higher than the substrate temperature during deposition of the upper insulating film to make the upper insulating film have therein a tensile stress.

10. The method of manufacturing the semiconductor device according to claim 9, wherein the substrate temperature during deposition at the step (b) is 400° C. or higher, the substrate temperature during deposition at the step (c) is 300° C. or lower, and the temperature of the heat treatment after deposition of the upper insulating film is 500° C. or higher.

11. The method of manufacturing the semiconductor device according to claim 8, wherein the lower insulating film and the upper insulating film are deposited at the steps (b) and (c) by plasma enhanced chemical vapor deposition by mixing gas which contains source elements of the lower insulating film and the upper insulating film with gas having a sputtering function.

12. The method of manufacturing the semiconductor device according to claim 11, wherein the lower insulating film and the upper insulating film are deposited at the steps (b) and (c) by using high density plasma generated by inductive coupling.

13. The method of manufacturing the semiconductor device according to claim 8, further comprising between the steps (b) and (c) a step of: (e) removing a surface layer of the lower insulating film.

14. The method of manufacturing the semiconductor device according to claim 13, wherein the surface layer of the lower insulating film is removed at the step (e) by chemical etching or sputtering.

15. The method of manufacturing the semiconductor device according to claim 8, further comprising between the steps (a) and (b) a step of: (f) forming a liner essentially consisting of silicon nitride film and covering an inner surface of the trench and an upper surface of the semiconductor substrate.