Patent Application
20250015127
Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly to field effect transistor (FET) devices.
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. There is always a need to improve the performance of semiconductor devices.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and may not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In addition, source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. For example, a device may include a first source/drain region and a second source/drain region, among other components. The first source/drain region may be a source region, whereas the second source/drain region may be a drain region, or vice versa. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Some of the features described below can be replaced or eliminated and additional features can be added for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
In recent development of semiconductor devices, particularly semiconductor devices having multiple active regions and transistors, gate connectors are often used to interconnect gate electrodes of transistors in different active regions. According to some embodiments of the present disclosure, a gate structure may have two gate electrode sections and a middle section that connects the two gate electrode sections. The two gate electrode sections may function as two gate electrodes respectively for two different transistors of a semiconductor device. Conventionally, the gate structure is homogeneous in composition. In other words, the gate electrode sections and the middle section are composed of the same material. A typical material of the homogenous gate structure is a work function metal, which usually has a relatively high resistivity. The overall resistance of the homogenous gate structure may be very high, at least in part due to the high resistivity of the middle section. The high resistance of the gate structure may cause many problems, such as overheating, unfavorable power dissipation, and low durability of functional elements in the semiconductor device.
In addition, an inter-layer dielectric (ILD) layer is usually formed to surround the gate structure and other conductive elements in the semiconductor device, according to some embodiments of the present disclosure. A conventional ILD layer is typically homogenous in composition and composed of a dielectric material having a relatively high dielectric constant (e.g., silicon dioxide). Parasitic capacitance may be generated between the gate structure and another conductive element proximate to the gate structure, at least in part due to the ILD layer filling in the gap therebetween. The parasitic capacitance is highly unfavorable and may also interfere with the nearby transistors and/or cause problems with the proper function of the active elements.
The present disclosure provides techniques to address the above-mentioned challenges. One insight provided in the present disclosure is related to a novel heterogeneous gate structure having a low-resistance section that connects the two gate electrode sections. According to some embodiments, the low-resistance section of the heterogeneous gate structure may have an enlarged width or cross-sectional dimension, compared with the gate electrode sections. The overall resistance of the heterogeneous gate structure can be significantly lowered due to the enlarged dimension of the low-resistance section, as compared with the conventional homogenous gate structure. According to some embodiments, the low-resistance section of the heterogeneous gate structure may be composed of a low-resistivity material that is different from the material of the gate electrode sections. The low-resistivity material may also contribute to the reduction of resistance for the heterogeneous gate structure. According to some embodiments, the low-resistance section may have a combination of both an enlarged dimension and a low-resistivity material. According to some embodiments, the semiconductor device may include multiple heterogeneous gate structures having the low-resistance section. The multiple low-resistance sections may significantly reduce the overall power dissipation and improve the performance of the semiconductor device.
Another insight provided in the present disclosure is a heterogeneous inter-layer dielectric (ILD) layer having different ILD structures that surround different sections of the heterogeneous gate structure in the semiconductor device. According to some embodiments, a heterogeneous ILD layer includes a first ILD structure that surrounds the gate electrode sections and a second ILD structure that surround the low-resistance section. The second ILD structure may be composed of a dielectric material having a relatively low dielectric constant and/or a relatively high dielectric strength, compared with the first ILD structure. The second ILD structure may fill a gap between two adjacent low-resistance sections or between a low-resistance section and another conductive element (e.g., a metal contact) adjacent to the low-resistance section. Accordingly, parasitic capacitance between the two adjacent low-resistance sections or between the low-resistance section and another conductive element may be significantly reduced. Additionally, the risk for electrical breakdown between the low-resistance section and another conductive element may be reduced or prevented due to the relatively high dielectric strength of the second ILD structure.
Example Semiconductor Devices with Heterogeneous Gate Structure
Various components or elements of the semiconductor device 100A are formed on the substrate 101. The elements of the semiconductor device 100A include active elements and/or passive elements. In at least one embodiment, active elements are arranged in a circuit region or a transistor region of the semiconductor device to provide one or more functions and/or operations intended to be performed by the semiconductor device 100A. In at least one embodiment, the semiconductor device 100A further includes a non-circuit region, e.g., a sealing region, that extends around and protects the circuit region. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors 125, 126 are described herein with respect to
The active regions 111 and 112 extend along the X-direction of the layout of the semiconductor device 100A. In some embodiments, the active regions 111 and 112 are also referred to as oxide-definition (OD) regions. Example materials of the active area regions 111 and 112 include, but are not limited to, semiconductor materials doped with various types of p-dopants and/or n-dopants. In at least one embodiment, the active regions 111 and 112 include dopants of the same type. In at least one embodiment, one of the active regions 111 and 112 includes dopants of a type different from a type of dopants of another one of the active regions 111 and 112. The active regions 111 and 112 may be isolated from each other by one or more gate isolation sections as described herein. In some embodiments, the active regions 111 and 112 are within corresponding well regions. For example, the active region 111 may be within a well region 113 which is an n-well region in one or more embodiments, and the active region 112 is within a well region 114 which is a p-well region in one or more embodiments. The described conductivity of the well regions 113 and 114 is an example. Other arrangements are within the scope of various embodiments.
The n-well region 113 and the p-well region 114 are on opposite sides of the imaginary line 110 which may divide the semiconductor device 100A into separate regions for different types of devices or transistors. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, gate-all-around (GAA) transistors, nanosheet transistors, or the like. In the illustrated example of
As illustrated in
The second gate electrode 118 further includes a gate dielectric layer 134 and a gate metal layer 136. The gate dielectric layer 134 is directly coupled to the channel region 132, and the gate metal layer 136 is disposed on the gate dielectric layer 134. Example materials of the gate metal layer 135, 136 include a metal or a polysilicon. In some embodiments, the metal of the gate electrodes 117 and 118 can be a work function metal such as tungsten (W), titanium nitride (TiN), titanium oxide (TiO), nickel silicide (NiSi), cobalt silicide (CoSi), hafnium (Hf), zirconium (Zr), aluminum (Al), and tantalum oxide (TaO). Other materials are within the scope of various embodiments. In some embodiments, the metal of the gate electrodes 117 and 118 has a relatively high resistivity, for example, at least 30 μΩ·cm, or at least 50 μΩ·cm, or at least 80 μΩ·cm. Non-limiting examples of the gate dielectric layer 133,134 include silicon dioxide, hafnium dioxide, aluminum oxide, silicon oxynitride (SiON), and so on. In some embodiments, the first and second transistors 125 and 126 are substantially aligned in the Y-direction. In some embodiments, two or more transistors are formed in each of the first and second circuit regions 121 and 122.
In some embodiments, two spacers (not shown) are formed and arranged along the sides (or boundaries) of the gate structure 103. The spacers may be disposed on the two opposite sides of both the gate electrodes 117 and 118 as well as the low-resistance section 140. The spacers may include one or more dielectric materials for electrically isolating the corresponding gate electrodes from unintended electrical contact. Example dielectric materials of the spacers include, but are not limited to, silicon nitride, silicon oxynitride, and silicon carbide. In at least one embodiment, one or more of the spacers have a tapered profile.
In some embodiments, the first and second transistors 125 and 126 are FinFETs. For example, a first fin 161 and a second fin 162 (as illustrated in
One or more shallow trench isolation (STI) structures 102 are formed on the substrate 101. Example materials of the STI structure 102 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, and/or combinations thereof. In an example, the formation of the STI structure 102 includes filling trenches between the fins, for example, by a chemical vapor deposition (CVD) process, with a dielectric material. In some embodiments, the filled trench has a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.
The semiconductor device 100A further includes an inter-layer dielectric (ILD) layer over the STI. In the example configuration in
The semiconductor device 100A may further include one or more via contacts disposed on the gate structure 103. As illustrated in
The gate structure 103 extends along the Y-direction, across the active regions 111 and 112. The gate structure 103 may include a plurality of gate electrodes separated and isolated by the low-resistance section 140. For example, the gate structure 103 includes the first gate electrode 117 and the second gate electrode 118. As described above, the first gate electrode 117 or a portion thereof is located in the first circuit region 121 and is a constituent of the first transistor 125. Likewise, the second gate electrode 118 or a portion thereof is located in the second circuit region 122 and is a constituent of the second transistor 126.
In the gate structure 103 of
In the illustrated example of
As described above, the low-resistance section 140 and the gate electrodes 117 and 118 are constituting sections of the gate structure 103. In some embodiments, the low-resistance section 140 is composed of a material that is the same or similar to the material of the gate electrodes 117 and 118. However, due to the larger width of the low-resistance section 140, the cross-sectional dimension (i.e., the cross-sectional area of the X-Z plane) of the low-resistance section 140 is larger compared with the first and second gate electrodes 117 and 118. Accordingly, the resistance of the heterogeneous gate structure 103 having the low-resistance section 140 can be significantly reduced compared with a homogenous gate structure without the low-resistance section 140 between the two gate electrodes. In some embodiments, the resistance of the heterogeneous gate structure 103 has a resistance reduction of at least 10%, at least 23%, at least 30%, at least 40%, at least 50%, or at least 75%, as compared with a homogenous gate structure without the low-resistance section 140.
In some embodiments, the gate electrodes 117 and 118 are composed of a first material, and the low-resistance section 140 is composed of a second material different from the first material. In some embodiments, the first material has a first resistivity, the second material has a second resistivity, and the second resistivity is less than the first resistivity. In some embodiments, the second resistivity is less than 100μΩ·cm, or less than 50μΩ·cm, or less than 30μΩ·cm, or less than 10μΩ·cm.
In the example of
In some embodiments, the first ILD structure 108 has a first dielectric constant and a first dielectric strength, and the second ILD structure 109 has a second dielectric constant and a second dielectric strength. In some embodiments, the second dielectric constant is lower than the first dielectric constant. In some embodiments, the second dielectric strength is higher than the first dielectric constant. In some embodiments, the second dielectric constant is lower than the dielectric constant of silicon dioxide. In some embodiments, the second dielectric constant is less than 4, less than 3.9, less than 3, or less than 2. In some embodiments, the second dielectric strength is higher than 0.001 V/μm, or higher than 1 V/μm, or higher than 10 V/μm, or higher than 100 V/μm, or higher than 400 V/μm. The low dielectric constant and/or high dielectric strength of the second ILD structure 109 surrounding the low-resistance section 140 may contribute to the reduction or prevention of parasitic capacitance between the low-resistance section 140 and another conductive element (e.g., another low-resistance section or a metal contact) adjacent to or in proximity to the low-resistance section 140. Accordingly, the combination of the low dielectric constant of the second ILD structure 109 and the low-resistivity material of the low-resistance section 140 may further improve the overall performance of the semiconductor device 100F.
In some embodiments, the low-resistance section 240 is surrounded by the second ILD structure 109 composed of a dielectric material different from the material of the first ILD structure 108. As described in the example of
The multiple gate structures 203a, 203b, and 203c respectively interconnect the transistors 125a and 126a, transistors 125b and 126b, and transistors 125c and 126c. The gate structure 203a further includes two gate electrodes 117a and 118a as well as a low-resistance section 240a between the two gate electrodes 117a and 118a. Likewise, the gate structure 203b further includes two gate electrodes 117b and 118b as well as a low-resistance section 240b between the two gate electrodes 117b and 118b, and the gate structure 203c further includes two gate electrodes 117c and 118c as well as a low-resistance section 240c between the two gate electrodes 117c and 118c. The gate electrodes 117a, 117b, and 117c are collectively labeled as gate electrodes 117, and the gate electrodes 118a, 118b, and 118c are collectively labeled as gate electrodes 118.
The multiple metal contacts 250a and 250b are respectively disposed between the gate structures 203a and 203b and between the gate structures 203b and 203c. As illustrated, due to the proximity between every two adjacent gate structures 203 (e.g., the gate structures 203a and 203b, or the gate structures 203b and 203c) the low-resistance sections 240 may be limited in width for the metal contacts 250 to be accommodated between the two adjacent gate structures 203. In some embodiments, the low-resistance sections 240 may have a width that is substantially the same as the width of the gate electrodes 117 and 118.
In the example of
The multiple gate structures 103a, 103b, 103c, 103d extend in the Y-direction and respectively interconnect the transistors 125a and 126a, transistors 125b and 126b, transistors 125c and 126c, and transistors 125d and 126d. The gate structure 103a further includes two gate electrodes 117a and 118a as well as a low-resistance section 140a between the two gate electrodes 117a and 118a. Likewise, the gate structure 103b further includes two gate electrodes 117b and 118b as well as a low-resistance section 140b between the two gate electrodes 117b and 118b; the gate structure 103c further includes two gate electrodes 117c and 118c as well as a low-resistance section 140c between the two gate electrodes 117c and 118c; the gate structure 103d further includes two gate electrodes 117d and 118d as well as a low-resistance section 140d between the two gate electrodes 117d and 118d. The gate electrodes 117a, 117b, 117c, and 117d are collectively labeled as gate electrodes 117; the gate electrodes 118a, 118b, 118c, and 118d are collectively labeled as gate electrodes 118; the low-resistance section 140a, 140b, 140c, and 140d are collectively labeled as low-resistance sections 140. The low-resistance sections 140 are similar to the low-resistance sections 140 shown in
In some embodiments, the two low-resistance sections 140 are substantially aligned in the X-direction. Every two adjacent gate structures 103 (e.g., the gate structures 103b and 103c) may have a distance (S0) characterized by the distance between the corresponding gate electrode sections in the same circuit region (e.g., the gate electrodes 117b and 117c in the first circuit region 321) in the X-direction. Every two adjacent gate structures 103 may have a spacing(S) characterized by the distance between the corresponding low-resistance sections 140 (e.g., the low-resistance sections 140b and 140c). As described above, the gate structure 103 may have a width (W0) characterized by the width of the gate electrode in the X-direction. The low-resistance section 140 may have a width (W) characterized by the distance between the two opposite sides thereof. In some embodiments, W is at least 10% more than W0. In some embodiments, a ratio of W to W0 (W/W0) is at least 2, at least 3, at least 4, or at least 5. In some embodiments, W/W0 is equal to or less than 5. In some embodiments, W/W0 is from 1.1 to 5. In some embodiments, S is at least 10% less than S0. In some embodiments, a ratio of S/S0 is no more than 0.9, no more than 0.6, or no more than 0.3. In some embodiments, S is equal to or more than W0. In some embodiments, a ratio of S/W0 is at least 1, at least 2, or at least 3. In some embodiments, S0, W0, and S satisfy the following relationship: 0.9*S0≥S≥W0. In some embodiments, S is at least 3 nm, at least 5 nm, at least 10 nm, or at least 15 nm. A minimum distance between every two adjacent low-resistance sections may ensure the proper function of the gate structure and minimize the risk of electrical breakdown between the adjacent low-resistance sections.
It should be noted that the values of W0, W, S0, and S may vary depending on design requirements. In some embodiments, the values of W0, W, S0, and S may be uniform or substantially uniform across the semiconductor device 300. In some embodiments, the values of W, S0, and S may vary across the semiconductor device 300. In some embodiments, a sum of the W of low-resistance section (e.g., the low-resistance section 140d) and the adjacent spacing S may be a constant (e.g., sum of the W0 of gate electrode sections 117d and S0 between the two corresponding gate electrode sections 117c and 117d). In other words, for each heterogenous gate structure 103 and an adjacent spacing S that are substantially the same, the W0, W, S0, and S of the heterogenous gate structures 103 and the adjacent spacing S may satisfy the following relationships: W+S=constant, or W+S=W0+S0.
In some embodiments, the low-resistance sections 140 may be composed of a material that is the same as or similar to the material of the gate electrodes 117 and 118. In some embodiments, the low-resistance sections 140 may be composed of a material that is different from the material of the gate electrodes 117 and 118. In some embodiments, the material of the low-resistance sections 140 may be a low-resistivity material. In some embodiments, the material of gate electrodes 117 and 118 has a first resistivity, and the material low-resistance sections 140 has a second resistivity. The second resistivity is less than the first resistivity.
In some embodiments, the ILD layer 107 of the semiconductor device 300 further includes a first ILD structure 108 and a second ILD structure 109, in a similar manner as the semiconductor device 100F. The gate electrodes 117 and 118 are respectively surrounded by the first ILD structure 108. The low-resistance sections 140 are surrounded by the second ILD structure 109. The second ILD structure 109 is composed of a material that is different from the material of the first ILD structure 108. In some embodiments, the second ILD structure 109 includes a material that has a relatively low dielectric constant (K) and/or a relatively high dielectric strength.
In some embodiments, the first ILD structure 108 has a first dielectric constant and a first dielectric strength, and the second ILD structure 109 has a second dielectric constant and a second dielectric strength. In some embodiments, the second dielectric constant is lower than the first dielectric constant. In some embodiments, the second dielectric strength is higher than the first dielectric constant. In some embodiments, the second dielectric constant is lower than the dielectric constant of silicon dioxide. In some embodiments, the second dielectric constant is less than 3.9. In some embodiments, the second dielectric strength is higher than 0.001 V/μm. In some embodiments, the low dielectric constant and/or high dielectric strength of the second ILD structure 109 between the two adjacent low-resistance sections (e.g., the low-resistance sections 140a and 140b) may contribute to the reduction or prevention of parasitic capacitance between the two low-resistance sections that are in proximity to each other. In addition, the relatively high dielectric strength of the second ILD structure 109 may also effectively prevent electric breakdown between the two adjacent low-resistance sections 140. Accordingly, the combination of the low dielectric constant of the second ILD structure 109 and the low-resistivity material of the low-resistance sections 140 may further improve the overall performance of the semiconductor device 300.
The multiple gate structures 403a, 403b, 403c, 403d extend in the Y-direction and respectively interconnect the transistors 125a and 126a, transistors 125b and 126b, transistor 125c and 126c, and transistors 125d and 126d. The gate structures 403a and 403b are similar to the gate structure 203 of
The metal contact 250 is disposed between the gate structures 403a and 403b. Similar to the metal contact 250 of
By contrast, the low-resistance sections 440c and 440d of the gate structures 403c and 403d have an enlarged width (e.g., W is larger than W0) and an enlarged cross-sectional dimension. In some embodiments, the low-resistance sections 440c and 440d may further include a material (e.g., a material with relatively lower resistivity) different from the material of the gate electrodes 117 and 118. Due to the proximity of the low-resistance sections 440c and 440d, no metal contact is disposed therebetween. Because of the multiple low-resistance sections 440, the overall performance of the semiconductor device 400 may be significantly improved.
In some embodiments, the layout of the semiconductor devices described herein is represented by a plurality of masks generated by one or more processors and/or stored in one or more non-transitory computer-readable media. Other formats for representing the layout of the semiconductor devices are within the scope of various embodiments. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. For example, the layout of the semiconductor device 400 is presented by at least one first mask corresponding to the active regions 111 and 112, at least one second mask corresponding to the gate structures 403a and 403b, at least one third mask corresponding to the gate structures 403c and 403d, at least one fourth mask corresponding to the low-resistance sections 440a and 440b, at least one fifth mask corresponding to the low-resistance sections 440a and 440b, at least one sixth mask corresponding to the low-resistance sections 440c and 440d, and at least one seventh mask corresponding to the metal contact 250.
In accordance with some aspects of the disclosure, semiconductor devices are provided. In one example, a semiconductor device includes: a substrate, a first circuit region and a second circuit region formed over the substrate and extending in a first direction, a first transistor located in the first circuit region. The first transistor includes a first gate electrode extending in a second direction, and the second direction is substantially perpendicular to the first direction. The semiconductor device further includes a second transistor located in the second circuit region. The second transistor includes a second gate electrode extending in the second direction and aligned with the first gate electrode in the second direction. The semiconductor device further includes a low-resistance section extending in the second direction and interconnecting the first and second gate electrodes. The low-resistance section is substantially aligned with the first and second gate electrodes in the second direction. The first and second gate electrodes have a first width (W0) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to W0 (W/W0) is at least 1.1.
In another example, a semiconductor device includes a substrate, a first circuit region and a second circuit region formed over the substrate and extending in a first direction, and a gate structure extending in a second direction that is substantially perpendicular to the first direction. The gate structure further includes: two gate electrode sections respectively located in the first and second circuit regions, and a low-resistance section between and interconnecting the two gate electrode sections. The two gate electrode sections are configured as gate electrodes for two transistors respectively located in the first and second circuit regions. The two gate electrode sections include a first material having a first resistivity, the low-resistance section includes a second material having a second resistivity, and the second resistivity is less than the first resistivity.
In yet another example, a semiconductor device includes a substrate, a first circuit region and a second circuit region formed over the substrate and extending in a first direction, and a plurality of gate structures extending in a second direction that is substantially perpendicular to the first direction. The plurality of gate structures further includes a first gate structure and a second gate structure adjacent to each other. The first gate structure further includes: a first gate electrode section and a second gate electrode section respectively located in the first and second circuit regions, and a first low-resistance section between and interconnecting the first and second gate electrode sections. The first and second gate electrode sections are configured as gate electrodes for a first transistor and a second transistor respectively located in the first and second circuit regions. The second gate structure further includes a third gate electrode section and a fourth gate electrode section respectively located in the first and second circuit regions, and a second low-resistance section between and interconnecting the third and fourth gate electrode sections. The third and fourth gate electrode sections are configured as gate electrodes for a third transistor and a fourth transistor respectively located in the first and second circuit regions. The first, second, third, and fourth gate electrode sections of the first and second gate structures have a first width (W0) along the first direction, the first and second low-resistance sections have a second width (W) along the first direction, and a ratio of W to W0 (W/W0) is at least 1.1.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
