Claims
- 1. A semiconductor memory comprising:
a memory mat having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; and an address comparing circuit enabled to store high and low logical values and a don't care value.
- 2. A semiconductor memory according to claim 1,
wherein said address comparing circuit comprises a first inverter, first and second P-channel MOS transistors, a plurality of first N-channel MOS transistors and a first plurality of bit comparing circuits, wherein the source/drain path of each of said first N-channel MOS transistors are coupled in series between a first node and a reference terminal, wherein said first and second P-channel transistors are coupled in parallel, via the source/drain paths thereof, between a voltage terminal and said first node, wherein the input of said first inverter is coupled to the said first node, and the output of said first inverter is coupled to the gate of said second P-channel MOS transistor, and wherein each said first plurality of bit comparing circuits has an output coupled to the gate of a respective one of said first N-channel MOS transistors.
- 3. A semiconductor memory according to claim 2,
wherein each bit comparing circuit has a fuse which can be blown by a laser beam.
- 4. A semiconductor memory according to claim 3,
wherein each bit comparing circuit further comprises an inverter, and first and second NAND gates which are cross-coupled.
- 5. A semiconductor memory according to claim 2,
wherein when the don't care value is stored in one of said bit comparing circuits, the input address signal is not compared with any data.
- 6. A semiconductor memory according to claim 2,
wherein said reference terminal is to be applied with reference ground.
- 7. A semiconductor memory according to claim 6,
wherein said first P-channel MOS transistor has a gate thereof to be applied with a precharge signal.
- 8. A semiconductor memory according to claim 2,
wherein said first P-channel MOS transistor has a gate thereof to be applied with a precharge signal.
- 9. A semiconductor memory according to claim 2,
wherein said address comparing circuit further comprises a plurality of second N-channel MOS transistors and a second plurality of bit comparing circuits, wherein the source/drain path of each of said second N-channel MOS transistors are coupled in series between said first node and said reference terminal, and wherein each of said second plurality of bit comparing circuits has an output coupled to the gate of a respective one of said second N-channel MOS transistors.
- 10. A semiconductor memory according to claim 9,
wherein each of the bit comparing circuits of said first and second plurality of bit comparing circuits has a fuse which can be blown by a laser beam.
- 11. A semiconductor memory according to claim 10,
wherein each of the bit comparing circuits of said first and second plurality of bit comparing circuits further comprises an inverter, and first and second NAND gates which are cross-coupled.
- 12. A semiconductor memory according to claim 9,
wherein when the don't care value is stored in one of the bit comparing circuits of said first and second plurality of bit comparing circuits, the input address signal is not compared with any data.
- 13. A semiconductor memory according to claim 9,
wherein said reference terminal is to be applied with reference ground.
- 14. A semiconductor memory according to claim 13,
wherein said first P-channel MOS transistor has a gate thereof to be applied with a precharge signal.
- 15. A semiconductor memory according to claim 9,
wherein said first P-channel MOS transistor has a gate thereof to be applied with a precharge signal.
Priority Claims (2)
Number |
Date |
Country |
Kind |
63-252028 |
Oct 1988 |
JP |
|
63-275375 |
Oct 1988 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of application Ser. No. 09/633,271, filed Aug. 4, 2000, which is a continuation of application Ser. No. 09/363,000, filed Jul. 30, 1999; which, in turn, is a continuation of application Ser. No. 09/144,258, filed Aug. 31, 1998, now U.S. Pat. No. 5,966,336; which is a continuation of application Ser. No. 08/825,605, filed Mar. 31, 1997, now U.S. Pat. No. 5,815,448; which, in turn is a continuation of application Ser. No. 08/535,574, filed Sep. 27, 1995 now U.S. Pat. No. 5,617,365; which, in turn, is a continuation of application Ser. No. 08/155,848, filed Nov. 23, 1993, now abandoned; which, in turn, is a divisional of application Ser. No. 07/818,434, filed Dec. 27, 1991, now U.S. Pat. No. 5,265,055; and which, in turn, is a continuation of application Ser. No. 07/419,399, filed Oct. 10, 1989, now abandoned; and the entire disclosures of which are incorporated herein by reference.
Divisions (1)
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07818434 |
Dec 1991 |
US |
Child |
08155848 |
Nov 1993 |
US |
Continuations (7)
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09633271 |
Aug 2000 |
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09992001 |
Nov 2001 |
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09363000 |
Jul 1999 |
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09633271 |
Aug 2000 |
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09144258 |
Aug 1998 |
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Child |
09363000 |
Jul 1999 |
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Parent |
08825605 |
Mar 1997 |
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Child |
09144258 |
Aug 1998 |
US |
Parent |
08535574 |
Sep 1995 |
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Child |
08825605 |
Mar 1997 |
US |
Parent |
08155848 |
Nov 1993 |
US |
Child |
08535574 |
Sep 1995 |
US |
Parent |
07419399 |
Oct 1989 |
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07818434 |
Dec 1991 |
US |