SEMICONDUCTOR DEVICE HAVING STACKED TRANSISTORS AND METHOD OF FORMING THE SAME

Abstract

A semiconductor device includes a first semiconductor layer, a first interlayer insulation layer, a second semiconductor layer, and a gate pattern. The first interlayer insulation layer covers the first semiconductor layer. The second semiconductor layer is formed on the first interlayer insulation layer and includes source regions, drain regions, and a channel region interposed between the source region and the drain region. The gate pattern includes a gate insulation layer on the channel region of the second semiconductor layer. At least one of the source regions and the drain regions includes an elevated layer having a top surface higher than that of the channel region.

Description

BRIEF DESCRIPTION OF THE FIGURES

Non-limiting and non-exhaustive embodiments will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified. In the figures:

FIG. 1 is a sectional view of a conventional semiconductor device having stacked transistors;

FIG. 2 is a sectional view of one embodiment of a semiconductor device having stacked transistors;

FIGS. 3A through 3F are sectional views illustrating an exemplary method of forming a semiconductor device having stacked transistors; and

FIGS. 4A and 4B are sectional views of exemplary applications of the semiconductor device described with respect to FIGS. 2 and 3A through 3F.

Claims

1. A semiconductor device, comprising: a first semiconductor layer;a first interlayer insulation layer covering the first semiconductor layer;a second semiconductor layer on the first interlayer insulation layer, the second semiconductor layer comprising a source region, a drain region and a channel region between the source and drain regions; anda gate pattern on the channel region,wherein at least one of the source and drain regions comprises an elevated layer, wherein a top surface of the elevated layer is above a top surface of the channel region.

2. The semiconductor device of claim 1, further comprising a first conducting column extending through the first interlayer insulation layer and the second semiconductor layer, wherein the first conducting column connects the first semiconductor layer and the second semiconductor layer and wherein a side portion of the first conducting column contacts the elevated layer.

3. The semiconductor device of claim 2, further comprising: a second interlayer insulation layer covering the second semiconductor layer; anda second conducting column extending through the second interlayer insulation layer, wherein a lower side portion of the second conducting column contacts the elevated layer.

4. The semiconductor device of claim 3, wherein the first and second conducting columns comprise a barrier layer and a conductor material surrounded by the barrier layer.

5. The semiconductor device of claim 1, further comprising a sidewall spacer on a sidewall of the gate pattern, wherein the elevated layer is self-aligned with respect to the sidewall spacer.

6. The semiconductor device of claim 5, further comprising a capping pattern on the gate pattern.

7. The semiconductor device of claim 6, wherein a crystal structure of the elevated layer corresponds to a crystal structure of the second semiconductor layer.

8. The semiconductor device of claim 1, wherein the source and drain regions and the elevated layer comprise an impurity of the same conductivity-type.

9. The semiconductor device of claim 8, wherein the source and drain regions comprise a low-concentration impurity region and a high-concentration impurity region formed in the low-concentration impurity region, wherein the high-concentration impurity region comprises the elevated layer and a portion of the second semiconductor layer adjacent to the elevated layer and wherein the high-concentration impurity region is separated from a bottom portion of the second semiconductor layer.

10. A method of forming a semiconductor device, the method comprising: forming a first interlayer insulation layer covering a first semiconductor layer;forming a second semiconductor layer on the first interlayer insulation layer;forming a source region, a drain region and a channel region between the source and drain regions within the second semiconductor layer;forming a gate pattern on the channel region; andforming an elevated layer on at least one of the source and drain regions, wherein a top surface of the elevated layer is above a top surface of the channel region.

11. The method of claim 10, further comprising forming a first conducting column extending through the second semiconductor layer and the first interlayer insulation layer, wherein the first conducting column connects the first semiconductor layer and the second semiconductor layer and wherein a side portion of the first conducting column contacts the elevated layer.

12. The method of claim 10, wherein forming the second semiconductor layer comprises: forming a plug in the first interlayer insulating layer, wherein the plug is connected to the first semiconductor layer; andforming a semiconductor material layer on the first interlayer insulation layer and on the plug, wherein a crystal structure of the semiconductor material layer corresponds to a crystal structure of the plug.

13. The method of claim 12, wherein a crystal structure of the plug corresponds to a crystal structure of the first semiconductor layer.

14. The method of claim 12, wherein forming the semiconductor material layer comprises: forming semiconductor material on the first interlayer insulation layer and contacting the plug, the semiconductor material comprising at least one of an amorphous and polycrystalline structure; andcrystallizing the semiconductor material.

15. The method of claim 12, wherein forming the semiconductor material layer comprises growing semiconductor material from the plug using a SEG method.

16. The method of claim 10, wherein forming the elevated layer comprises: forming a sidewall spacer on a sidewall of the gate pattern, wherein a portion of the second semiconductor layer is exposed by the sidewall spacer; andselectively forming a semiconductor material on the second semiconductor layer and adjacent to the sidewall spacer.

17. The method of claim 16, wherein forming the gate pattern comprises: forming a gate insulation layer, a gate conductor layer and a capping layer on the second semiconductor layer; andpatterning the capping layer and the gate conductor layer to form a capping pattern and a gate electrode pattern, respectively.

18. The method of claim 16, wherein forming the source and drain regions comprises introducing a first concentration of an impurity into the second semiconductor layer before forming the sidewall spacer using the gate pattern as a mask.

19. The method of claim 18, wherein forming the source and drain regions further comprises: introducing a second concentration of an impurity into the elevated layer using the sidewall spacer as a mask, the second concentration being higher than the first concentration; anddiffusing the second concentration of the impurity from the elevated layer into a portion of the second semiconductor layer adjacent to the elevated layer such that the impurity diffused from the elevated layer is separated from a bottom portion of the second semiconductor layer.

20. The method of claim 11, wherein forming the first conducting column comprises: forming a first contact hole through the second semiconductor layer and the first interlayer insulation layer exposing the first semiconductor layer; anddepositing a conductive material within the first contact hole,wherein a side portion of the first conducting column contacts the elevated layer.

21. The method of claim 20, further comprising: forming a second interlayer insulation layer covering the second semiconductor layer;forming a second hole through the second interlayer insulation layer exposing the source or drain region; anddepositing a conductive material within the second contact hole, thereby forming a second conducting column,wherein a lower side portion of the second conducting column contacts the elevated layer.