SEMICONDUCTOR DEVICE INCLUDING DIFFERENT CONDUCTIVE LINES

Abstract

A semiconductor device includes a lower structure, an interlayer insulating layer on the lower structure, a conductive shielding line on the lower structure and penetrating through the interlayer insulating layer, a capping insulating layer on the interlayer insulating layer and the conductive shielding line, and a bit line on the lower structure and penetrating through the capping insulating layer and the interlayer insulating layer. An upper surface of the bit line is at a higher level than an upper surface of the conductive shielding line. A lower surface of the bit line is at a level equal to or lower than a level of a lower surface of the conductive shielding line.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2022-0114379 filed on Sep. 8, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field

Example embodiments relate to a semiconductor device including different conductive lines and a method of manufacturing the same.

2. Description of the Related Art

Research has been conducted to reduce the size of elements included in a semiconductor device and to improve the performance thereof. With a reduction in the size of the elements included in the semiconductor device, RC delay, which is caused by parasitic capacitance between bit lines, has emerged as a big issue with respect to bit lines that have a reduced size.

SUMMARY

Embodiments are directed to a semiconductor device including a lower structure an interlayer insulating layer on the lower structure, a conductive shielding line on the lower structure, the conductive shielding line penetrating through the interlayer insulating layer, a capping insulating layer on the interlayer insulating layer and the conductive shielding line, and a bit line on the lower structure, the bit line penetrating through the capping insulating layer and the interlayer insulating layer, wherein an upper surface of the bit line is at a higher level than an upper surface of the conductive shielding line, and a lower surface of the bit line is at a level equal to or lower than a level of a lower surface of the conductive shielding line.

Embodiments further include a semiconductor device including a lower structure, a first conductive line on the lower structure; and a second conductive line on the lower structure and spaced apart from the first conductive line, wherein an upper surface of the second conductive line is at a higher level than an upper surface of the first conductive line, a lower surface of the second conductive line is at a level the same as or lower than a level of a lower surface of the first conductive line, and a slope of a side surface of the second conductive line is different from a slope of a side surface of the first conductive line.

Embodiments further include a semiconductor device including a substrate, a circuit device on the substrate, a wiring structure on the substrate and electrically connected to the circuit device, bit lines respectively extending in a first horizontal direction, and at a level higher than level of the wiring structure, conductive shielding lines arranged alternately with the bit lines in a second horizontal direction perpendicular to the first horizontal direction, and word lines respectively extending in the second horizontal direction, wherein the word lines are at a higher level than the bit lines and the conductive shielding lines upper surfaces of the bit lines are at a higher level than upper surfaces of the conductive shielding lines, and each of the bit lines has a negative slope.

BRIEF DESCRIPTION OF DRAWINGS

Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

FIGS. 1, 2A and 2B are schematic views illustrating an example of a semiconductor device according to an example embodiment;

FIG. 3 is a schematic cross-sectional view illustrating a modification of a semiconductor device according to an example embodiment;

FIG. 4 is a schematic cross-sectional view illustrating a modification of a semiconductor device according to an example embodiment;

FIG. 5 is a schematic cross-sectional view illustrating a modification of a semiconductor device according to an example embodiment;

FIG. 6 is a schematic cross-sectional view illustrating a modification of a semiconductor device according to an example embodiment;

FIG. 7 is a schematic cross-sectional view illustrating a modification of a semiconductor device according to an example embodiment;

FIG. 8 is a schematic cross-sectional view illustrating a modification of a semiconductor device according to an example embodiment;

FIGS. 9A and 9B are schematic views illustrating modifications of a semiconductor device according to an example embodiment;

FIG. 10 is a schematic process flowchart illustrating an example of a method of manufacturing a semiconductor device according to example embodiments; and

FIGS. 11A to 11D are schematic cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to an example embodiment.

DETAILED DESCRIPTION

Herein, an example of a semiconductor device according to example embodiments of the present disclosure is described with reference to FIGS. 1, 2A, and 2B. FIGS. 1, 2A, and 2B are schematic views illustrating an example of a semiconductor device according to an example embodiment of the present disclosure. FIG. 1 is a schematic plan view illustrating an example of a semiconductor device according to an example embodiment of the present disclosure. FIG. 2A is a cross-sectional view illustrating a region taken along line I-I′ of FIG. 1. FIG. 2B is a cross-sectional view illustrating a region taken along line II-IF of FIG. 1.

Referring to FIGS. 1, 2A, and 2B, a semiconductor device 1 according to an example embodiment may include a lower structure LS, an interlayer insulating layer 54 on the lower structure LS, first conductive lines 57a passing through the interlayer insulating layer 54, a capping insulating layer 61 on the interlayer insulating layer 54 and the first conductive lines 57a, and second conductive lines 64a passing through the capping insulating layer 61 and the interlayer insulating layer 54.

The lower structure LS may include a substrate 3, a circuit device TR on the substrate 3, a lower insulating structure 34 covering the circuit device TR on the substrate 3, and a wiring structure 18 electrically connected to the circuit device TR on the substrate 3 and buried in the lower insulating structure 34.

The substrate 3 may be a semiconductor substrate. For example, the substrate 3 may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. For example, the substrate 3 may include a silicon material, for example, a single crystal silicon material. The substrate 3 may be a silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

The circuit device TR may include a peripheral transistor. For example, the peripheral transistor may include a gate structure 12 disposed on a peripheral active region 9a defined by an isolation region 9b in the substrate 3, and peripheral source/drain regions 15 disposed in the peripheral active region 9a on opposite sides of the gate structure 12.

The gate structure 12 may include a peripheral gate electrode 12b and a peripheral gate dielectric layer 12a between the peripheral gate electrode 12b and the peripheral active region 9a. The peripheral gate electrode 12b may include at least two conductive layers, for example, a first conductive layer 12b1 and a second conductive layer 12b2 on the first conductive layer 12b1.

The lower insulating structure 34 may include a plurality of insulating layers 37, 39, 41, 43, 45, and 47. For example, the plurality of insulating layers 37, 39, 41, 43, 45, and 47 may include a first insulating layer 37, a second insulating layer 39, a third insulating layer 41, a fourth insulating layer 43, a fifth insulating layer 45, and a sixth insulating layer 47 being sequentially stacked. The first insulating layer 37 may be disposed on a side surface of the peripheral gate electrode 12b, and the second insulating layer 39 may cover the first insulating layer 37 and the peripheral gate electrode 12b.

The wiring structure 18 may include a first plug 21 electrically connected to the circuit device TR, a first connection pattern 23 on the first plug 21, a second plug 25 on the first connection pattern 23, a second connection pattern 27 on the second plug 25, and a first contact plug 29 on the second connection pattern 27. The first and second insulating layers 37 and 39 may surround side surfaces of the first plug 21 and the first connection pattern 23. The third insulating layer 41 may surround a side surface of the second plug 25. The fourth insulating layer 43 may surround a side surface of the second connection pattern 27. The fifth and sixth insulating layers 45 and 47 may surround a side surface of the first contact plug 29.

The first contact plug 29 may include a conductive pattern 29b and a barrier layer 29a covering a side surface and a bottom surface of the conductive pattern 29b.

The fifth insulating layer 45 may be an etch stop layer having a thickness less than that of the sixth insulating layer 47, the etch stop layer including a material different from that of the sixth insulating layer 47. For example, the sixth insulating layer 47 may include silicon oxide or a low-K dielectric, and the fifth insulating layer 45 may include an insulating material such as SiN, SiCN, or SiBN.

A thickness of the capping insulating layer 61 may be less than a thickness of the interlayer insulating layer 54.

The interlayer insulating layer 54 may include silicon oxide or a low-x dielectric.

In an example, the capping insulating layer 61 may include a material the same as that of the interlayer insulating layer 54.

In another example, the capping insulating layer 61 may include a material different from that of the interlayer insulating layer 54. For example, the capping insulating layer 61 may include an insulating material such as SiN, SiCN, or SiBN.

Each of the first conductive lines 57a may extend in a first horizontal direction X. Each of the second conductive lines 64a may extend in the first horizontal direction X. The first conductive lines 57a may be repeatedly arranged alternately with the second conductive lines 64a in a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be parallel to an upper surface of the substrate 3. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other.

In an example embodiment, the first conductive lines 57a may serve to screen capacitive coupling between the second conductive lines 64a. For example, the first conductive lines 57a may reduce or block parasitic capacitance between the second conductive lines 64a, thereby minimizing RC delay of the second conductive lines 64a. The first conductive lines 57a may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO_x, RuO_x, graphene, carbon nanotubes, or combinations thereof. The first conductive lines 57a may include a single layer or multiple layers formed of the above-described materials.

In an example embodiment, the second conductive lines 64a may be bit lines of a memory device. Accordingly, the second conductive lines 64a may be referred to as bit lines, and the first conductive lines 57a may be shielding lines or shield patterns screening capacitive coupling between bit lines. The first conductive lines 57a may be referred to as conductive shielding lines or conductive shield patterns.

Hereinafter, “the first conductive lines 57a” will be referred to as “conductive shielding lines,” and “the second conductive lines 64a” will be referred to as bit lines. In addition, hereinafter, one conductive shielding line 57a and one bit line 64a adjacent to each other will mainly be described.

An upper surface of the bit line 64a may be on a level higher than the level of an upper surface of the conductive shielding line 57a.

In an example, a lower surface of the bit line 64a may be on a level substantially the same as the level of a lower surface of the conductive shielding line 57a.

The bit line 64a may include doped polysilicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a metal compound, a conductive metal oxide, graphene, carbon nanotubes, or combinations thereof. For example, the bit line 64a may include a conductive pattern 65b and a barrier layer 65a covering a side surface and a bottom surface of the conductive pattern 65b. For example, the barrier layer 65a may include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN, and the conductive pattern 65b may include a metal material such as W or Mo.

As a non-limiting example, the first conductive line 57a may include at least one of the materials of the bit line 64a, but the example embodiments are not limited thereto. In some implementations, the first conductive line 57a may include a conductive material that is different from the materials of the bit line 64a.

The bit line 64a may be electrically connected to the first contact plug 29 while being in contact therewith. For example, the barrier layer 65a of the bit line 64a may be in contact with the first contact plug 29.

A width of the bit line 64a may be greater than the width of the first contact plug 29.

In an example, the width of the bit line 64a may be substantially equal to a width of the conductive shielding line 57a.

In another example, the width of the bit line 64a may be greater than the width of the conductive shielding line 57a.

Referring to FIG. 2B, the semiconductor device 1 may further include an upper structure US. The upper structure US may include a channel structure 73, word lines 79, data storage structures 87, and an upper insulating structure 84.

The channel structure 73 may be disposed on the bit line 64a. The channel structure 73 may include a horizontal portion 73L electrically connected to the bit line 64a while being in contact therewith, and a first vertical channel portion 73S1 and a second vertical channel portion 73S2 extending in a vertical direction Z from opposite sides of the horizontal portion 73L in the first horizontal direction X. The vertical direction Z may be a direction that is perpendicular to the upper surface of the substrate 3.

The channel structure 73 may be formed of a semiconductor material such as silicon or the like. The channel structure 73 may be formed of single crystal silicon or polysilicon. The channel structure 73 is not limited to a semiconductor material such as silicon or the like, and the channel structure 73 may be formed of another semiconductor material that is usable as a channel region of a transistor. For example, the channel structure 73 may include an oxide semiconductor layer or a two-dimensional (2D) material layer that is usable as a channel region of a transistor.

The oxide semiconductor layer may be indium gallium zinc oxide (IGZO). However, the example embodiment are not limited thereto. As non-limiting examples, the oxide semiconductor layer may include at least one of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc, zinc oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

The 2D material layer may include at least one of a transition metal dichalcogenide (TMD) material layer, a black phosphorous material layer, and a hexagonal boron-nitride (hBN) material layer, which may have semiconductor properties. For example, the 2D material layer may include at least one of BiOSe, Cr1, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and a Janus 2D material, which may form a 2D material.

Each of the word lines 79 may extend in the second horizontal direction Y. A pair of word lines 79a and 79b among the word lines 79 may vertically overlap the horizontal portion 73L of the channel structure 73, and may be disposed between the first and second vertical channel portions 73S1 and 73 S2 of the channel structure 73. The pair of word lines 79a and 79b may include a first word line 79a opposing the first vertical channel portion 73S1 and a second word line 79b opposing the second vertical channel portion 73S2.

The upper structure US may further include dielectric structures 76 between the word lines 79 and the channel structure 73. The dielectric structures 76 may include a first dielectric structure 76a, which may be disposed between the first word line 79a and the first vertical channel portion 73S1 and between the first word line 79a and the horizontal portion 73L, and a second dielectric structure 76b, which may be disposed between the second word line 79b and the second vertical channel portion 73S2 and between the second word line 79b and the horizontal portion 73L.

In an example, each of the dielectric structures 76 may be a tunnel dielectric layer not including a data storage layer. For example, each of the dielectric structures 76 may include at least one of silicon oxide and a high-K dielectric. The high-K dielectric may include a metal oxide or a metal oxynitride. For example, the high-K dielectric may be formed of HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO₂, Al₂O₃, or combinations thereof, as non-limiting examples. Each of the dielectric structures 76 may be formed of a single layer or multiple layers formed of the above-described materials.

In another example, each of the dielectric structures 76 may include a data storage layer and a dielectric layer. For example, each of the dielectric structures 76 may include a ferroelectric layer, which may have polarization properties according to an electric field and may have remnant polarization due to a dipole even in the absence of an external electric field. Data may be recorded using a polarization state in the ferroelectric layer. Accordingly, each of the dielectric structures 76 may include a ferroelectric layer, which may be referred to as a data storage layer. The ferroelectric layer, which may be the data storage layer, may include an Hf-based compound, a Zr-based compound, and/or an Hf—Zr-based compound. For example, the Hf-based compound may be an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf—Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer, which may be the data storage layer, may include a ferroelectric material doped with an impurity, for example, at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr. For example, the ferroelectric layer, which may be the data storage layer, may be a material obtained by doping at least one of HfO₂, ZrO₂, and HZrO with at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr.

In the dielectric structures 76, the data storage layer is not limited to the above-described types of materials, and the data storage layer may include a material capable of storing information.

The upper structure US may further include landing pads 81 electrically connected to each of the first and second vertical channel portions 73S1 and 73S2 while being in contact therewith, on the channel structure 73. The landing pads 81 may be formed of a conductive material.

The upper insulating structure 84 may be disposed on the bit lines 64a and the capping insulating layer 61. The upper insulating structure 84 may cover a side surface of a structure including the channel structure 73, the word lines 79, and the landing pads 81.

The data storage structure 87 may include first electrodes 88a electrically connected to the landing pads 81 while being in contact therewith, a second electrode 88c on the first electrodes 88a, and a dielectric layer 88b between the first electrodes 88a and the second electrode 88c.

In an example, the data storage structure 87 may be a capacitor in which a DRAM stores information. For example, the dielectric layer 88b of the data storage structure 87 may be a capacitor dielectric layer of the DRAM, and the dielectric layer 88b may be a high-K dielectric layer. As non-limiting examples, the material of the dielectric layer 88b may be silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

In another example, the data storage structure 87 may be a structure for storing information, at a memory different from the DRAM. For example, the data storage structure 87 may be a capacitor of a ferroelectric memory (FeRAM). For example, the dielectric layer 88b may be a ferroelectric layer capable of recording data using a polarization state. In another example, the dielectric layer 88b may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. Here, the lower dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-x dielectric.

In an example embodiment, when the dielectric structures 76 include a data storage layer, the data storage structure 87 may be omitted.

Hereinafter, various modifications of elements of the above-described example embodiment will be described. The various modifications of the elements of the above-described example embodiment described below will mainly be described with respect to elements to be modified or elements to be replaced. In addition, the elements that are modifiable or replaceable to be described below are described with reference to drawings below, but the elements that are modifiable or replaceable may be combined with each other, or may be combined with the elements described above to configure a semiconductor device according to example embodiments.

FIGS. 3, 4, 5, 6, 7, and 8 are schematic cross-sectional views illustrating a modification of a semiconductor device according to an example embodiment of the present disclosure. FIGS. 3, 4, 5, 6, 7, and 8 illustrate various modifications of a cross-sectional structure of a region taken along line I-I′ of FIG. 1.

In a modification, referring to FIG. 3, the bit line (64a in FIG. 2A) having a substantially vertical side surface illustrated in FIG. 2A may be modified as a bit line 64b having a side surface 64_Sa having a negative slope, as illustrated in FIG. 3. The bit line 64b may have the side surface 64_Sa inclined such that a width thereof gradually decreases from an upper region thereof to a lower region thereof.

The conductive shielding line (57a in FIG. 2A) having a substantially vertical side surface illustrated in FIG. 2A may be modified as a conductive shielding line 57b having a side surface 57_Sa having a positive slope. The conductive shielding line 57b may have the side surface 57_Sa inclined such that a width thereof gradually increases from an upper region thereof to a lower region thereof.

A width of the bit line 64b may be greater than that of the conductive shielding line 57b. A maximum width of the bit line 64b may be greater than a maximum width of the conductive shielding line 57b. A minimum width of the bit line 64b may be equal to or greater than the maximum width of the conductive shielding line 57b.

In some implementations, referring to FIG. 4, the conductive shielding line (57a in FIG. 2A) in FIG. 2A or the conductive shielding line (57b in FIG. 3) in FIG. 3 may be modified into a conductive shielding line 57c including a sequentially stacked shield barrier layer 56a and a shield conductive pattern 56b on the shield barrier layer 56a.

The shield barrier layer 56a may include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN, and the shield conductive pattern 56b may include a metal material such as W or Mo.

The conductive shielding line 57c may have a side surface 57_Sb having a positive slope, as described with reference to FIG. 3. A side surface of the shield conductive pattern 56b may be in contact with the interlayer insulating layer 54. A thickness of the shield conductive pattern 56b may be greater than a thickness of the shield barrier layer 56a.

In a modification, referring to FIG. 5, the bit line (64a in FIGS. 2A and 64b in FIGS. 3 and 4) described above may be modified into a bit line 64c covering an upper surface and a side surface of an upper region of the first contact plug 29, as illustrated in FIG. 5. For example, the semiconductor device 1 may include the bit line 64c, together with the conductive shielding line 57c described with reference to FIG. 4.

As illustrated in FIG. 5, the bit line 64c may have a side surface 64_Sa having a negative slope, and a lowermost end of the bit line 64c may be disposed on a level lower than that of a lowermost end of the conductive shielding line 57c.

In a modification, referring to FIG. 6, the lower structure LS may further include an etch stop layer 51 on the interlayer insulating layer 47. The etch stop layer 51 may include a material different from that of the interlayer insulating layer 47. For example, the interlayer insulating layer 47 may include silicon oxide or a low-x dielectric, and the etch stop layer 51 may include an insulating material such as SiN, SiCN, or SiBN.

The first contact plug 29 may pass through the interlayer insulating layer 47 and the etch stop layer 51. The conductive shielding line (57a in FIG. 2A, 57b in FIG. 3, and 57c in FIG. 4) and the bit line (64a in FIGS. 2A and 64b in FIGS. 3 and 4) described above with reference to FIGS. 2A, 3, and 4 may be disposed on the etch stop layer 51. For example, the bit line 64b illustrated in FIG. 6 may be disposed on the etch stop layer 51 electrically connected to the first contact plug 29 while being in contact therewith. A lower surface of the conductive shielding line 57c illustrated in FIG. 6 may be in contact with an upper surface of the etch stop layer 51.

In an embodiment, referring to FIG. 7, a portion of the bit line (64a in FIGS. 2A, 64b in FIGS. 3 and 4, and 64b in FIG. 6) in contact with the first contact plug 29 may be modified into a bit line 64d in FIG. 7. For example, a lower surface 64d_L of the bit line 64d in contact with the first contact plug 29 may have a downwardly curved shape.

In a modification, referring to FIG. 8, the bit line (64b in FIG. 6) disposed on the etch stop layer 51 described above with reference to FIG. 6 may be modified into a bit line 64e passing through the etch stop layer 51. The bit line 64e may pass through the etch stop layer 51 and may be in contact with the interlayer insulating layer 47 and the first contact plug 29. A lower surface 64e_L of the bit line 64e may be disposed on a level lower than that of an upper surface of the etch stop layer 51. As described with reference to FIG. 6, the conductive shielding line 57c may be disposed on the etch stop layer 51. The lower surface 64e_L of the bit line 64e may be disposed on a level lower than that of the lower surface of the conductive shielding line 57c. An upper surface of the first contact plug 29 may be disposed on a level lower than that of the lower surface of the conductive shielding line 57c.

Subsequently, with reference to FIGS. 9A and 9B, modifications of the conductive shielding line (57a in FIGS. 1 and 2A) and the wiring structure 18 will be described. FIG. 9A is a schematic plan view illustrating a modification of the conductive shielding line (57a in FIG. 1) in FIG. 1, and FIG. 9B is a schematic cross-sectional view illustrating a region taken along line in FIG. 1.

In a modification, referring to FIGS. 9A and 9B, the wiring structure (18 in FIG. 2A) described above may be modified into a wiring structure 118 further including a second contact plug 31, and the conductive shielding line (57a in FIGS. 1 and 2A) described above may be modified into a conductive shielding line 157 electrically connected to the second contact plug 31. The second contact plug 31 may include a conductive pattern 30b and a barrier layer 30a covering a side surface and a bottom surface of the conductive pattern 30b.

The wiring structure 118 may include the first contact plug 29 as described with reference to FIGS. 1, 2A, and 2B. The first contact plug 29 of the wiring structure 118 may be electrically connected to one bit line among the bit lines (64a in FIGS. 1 to 2B, 64b in FIGS. 3A, 4, and 6, 64c in FIG. 5, 64d in FIG. 7, and 64e in FIG. 8), for example, the bit line 64a described with reference to FIGS. 1, 2A, and 2B.

The second contact plug 31 and the conductive shielding line 157 described with reference to FIGS. 9A and 9B may be described in various combinations with all the example embodiments described above. For example, the wiring structure 18 of the example embodiments described with reference to FIGS. 3 to 8 may be modified into the wiring structure 118 including the second contact plug 3 illustrated in FIGS. 9A and 9B. The conductive shielding line (57b in FIGS. 3 and 57c in FIGS. 4 to 8) of the example embodiments described with reference to FIGS. 3 to 8 may be modified into the conductive shielding line 157 electrically connected to the second contact plug 31 illustrated in FIGS. 9A and 9B.

Subsequently, an example of a method of forming a semiconductor device according to an example embodiment of the present disclosure will be described with reference to FIGS. 1, 10, and 11A to 11D. FIG. 10 is a schematic process flowchart illustrating an example of a method of forming a semiconductor device according to an example embodiment of the present disclosure, and FIGS. 11A to 11D are schematic cross-sectional views illustrating a region taken along line I-I′ of FIG. 1 so as to describe an example of a method of forming a semiconductor device according to an example embodiment of the present disclosure.

Referring to FIGS. 1, 10 and 11A, a lower structure LS may be formed (S10). The lower structure LS may include the substrate 3, the circuit device TR on the substrate 3, the lower insulating structure 34 covering the circuit device TR on the substrate 3, and the wiring structure 18, electrically connected to the circuit device TR and buried in the lower insulating structure 34, on the substrate 3, as described with reference to FIGS. 2A and 2B.

The wiring structure 18 may include the first contact plug 29, as described with reference to FIG. 2A.

The wiring structure 18 may be modified into the wiring structure (118 in FIGS. 9A and 9B) further including the second contact plug 31, as described with reference to FIGS. 9A and 9B.

A conductive shield layer 56 may be formed on the lower structure LS (S20).

In an example, the conductive shield layer 56 may be formed of a single material layer.

In another example, the conductive shield layer 56 may be formed of a plurality of material layers sequentially stacked. For example, the conductive shield layer 56 may include a first material layer 56a and a second material layer 56b on the first material layer 56a. The first material layer 56a may be a barrier layer.

In another example, before the conductive shield layer 56 is formed, an etch stop layer (51 in FIGS. 6 to 8) may be formed, as illustrated in FIGS. 6 to 8. Here, the conductive shield layer 56 may be formed on the etch stop layer (51 in FIGS. 6 to 8). The etch stop layer (51 in FIGS. 6 to 8) may include an insulating material such as SiN, SiCN or SiBN.

A mask pattern 58 may be formed on the conductive shield layer 56. The mask pattern 58 may be a photoresist pattern.

Referring to FIGS. 1, 10, and 11B, the conductive shield layer 56 may be patterned to form conductive shielding lines 57c (S30). Forming the conductive shielding lines 57c may include etching the conductive shield layer (56 in FIG. 11A) by an etching process using the mask pattern (58 in FIG. 11A) as an etch mask, and removing the mask pattern (58 in FIG. 11A).

In an implementation, the conductive shielding lines 57c may be the conductive shielding lines (57c in FIG. 4) described with reference to FIG. 4, but example embodiments are not limited thereto. For example, the conductive shielding lines 57c may be formed as conductive shielding lines (57a in FIG. 2A) illustrated in FIG. 2A or conductive shielding lines (57b in FIG. 3).

In another example, when an etch stop layer (51 in FIGS. 6 to 8) is formed as illustrated in FIGS. 6 to 8 before the conductive shield layer (56 in FIG. 11A) is formed, the conductive shielding lines 57c may be formed as the conductive shielding lines (57c in FIGS. 6 to 8), as illustrated in FIGS. 6 to 8.

Referring to FIGS. 1, 10, and 11C, an interlayer insulating layer 54 may be formed between the conductive shielding lines 57c (S40). Forming the interlayer insulating layer 54 may include an forming an insulating layer filling in between the conductive shielding lines 57c and covering the conductive shielding lines 57c, and planarizing the insulating layer until upper surfaces of the conductive shielding lines 57c are exposed.

A capping insulating layer 61 may be formed on the conductive shielding lines 57c and the interlayer insulating layer 54 (S50). A thickness of the capping insulating layer 61 may be less than a thickness of the interlayer insulating layer 54.

In some implementations, the interlayer insulating layer 54 and the capping insulating layer 61 may be formed of the same material, for example, silicon oxide or a low-x dielectric.

In some implementations, the interlayer insulating layer 54 and the capping insulating layer 61 may be formed of different materials. For example, the interlayer insulating layer 54 may be formed of silicon oxide, a low-x dielectric, or a silicon oxide-based material, and the capping insulating layer 61 may be formed of an oxide-based material different from that of the interlayer insulating layer 54 or a silicon nitride-based material.

The capping insulating layer 61 may be a planarization stop layer. For example, the capping insulating layer 61 may be a planarization stop layer in a chemical mechanical polishing process.

Referring to FIGS. 1, 10 and 11D, trenches 63, passing through the capping insulating layer 61 and the interlayer insulating layer 54, may be formed between the conductive shielding lines (S60). The trenches 63 may expose the first contact plugs 29.

In another example, the trenches 63 may pass through the interlayer insulating layer 54 and extend into the sixth insulating layer 47 to expose upper regions of the first contact plugs 29.

In another example, when an etch stop layer (51 in FIG. 6) is formed as illustrated in FIG. 6 before the conductive shield layer (56 in FIG. 11A) is formed, the trenches 63 may expose the etch stop layer (51 in FIG. 6). Here, the first contact plugs 29 may include a portion passing through the etch stop layer (51 in FIG. 6), and may be exposed by the trenches 63.

In another example, when an etch stop layer (51 in FIG. 7) is formed as illustrated in FIG. 7 before the conductive shield layer (56 in FIG. 11A) is formed, the trenches 63 may expose the etch stop layer. (51 in FIG. 7). Here, the first contact plugs 29 may include a portion passing through the etch stop layer (51 in FIG. 7), and the trenches 63 may expose the etch stop layer (51 in FIG. 7), and may expose upper surfaces of the first contact plugs 29 while recessing the upper surfaces of the first contact plugs 29.

In another example, when an etch stop layer (51 in FIG. 8) is formed as illustrated in FIG. 8 before the conductive shield layer (56 in FIG. 11A) is formed, the trenches 63 may pass through the etch stop layer (51 in FIG. 8). Here, the first contact plugs 29 may be formed below the etch stop layer (51 in FIG. 8), and the trenches 63 may expose the first contact plugs 29 while passing through the etch stop layer (51 in FIG. 8).

Referring to FIGS. 1, 10, and 4, bit lines (64b in FIG. 4) may be formed in the trenches (63 in FIG. 11D) (S70).

Forming the bit lines 64b may include forming a first material layer 65a conformally covering inner walls of the trenches (63 in FIG. 11D) and an upper surface of the capping insulating layer 61, forming a second material layer 65b filling the trenches (63 in FIG. 11D) on the first material layer 65a, and planarizing the first and second material layers 65a and 65b until the upper surface of the capping insulating layer 61 is exposed. The planarization may be a chemical mechanical polishing process, and the capping insulating layer 61 may be a planarization stop layer. The first material layer 65a may be a barrier layer.

The bit lines 64b may be the bit lines (64b in FIG. 4) described with reference to FIG. 4, as non-limiting examples. For example, depending on various forms of the trenches 63 described with reference to FIG. 11D, the bit lines 64b may be the bit lines (64a in FIGS. 1, 2A, and 2B) described with reference to FIGS. 1, 2A, and 2B, the bit lines (64b in FIG. 3) described with reference to FIG. 3, the bit lines (64c in FIG. 5) described with reference to FIG. 5, the bit lines (64b in FIG. 6) described with reference to FIG. 6, the bit lines (64d in FIG. 7) described with reference to FIG. 7, or the bit lines (64e in FIG. 8) described with reference to FIG. 8.

Referring to FIGS. 1, 10, 2A, and 2B, an upper structure US may be formed on the capping insulating layer 61 and the bit lines 64a (S80). As illustrated in FIG. 2B, the upper structure US may include the channel structure 73, the dielectric structure 76, the word lines 79, the landing pads 81, the upper insulating structure 84, and the data storage structure 87. However, a form of the upper structure US is not limited to the example embodiment illustrated in FIG. 2B, and may be modified in various manners.

According to example embodiments, as illustrated in FIGS. 11A and 11B, the conductive shielding lines (57c in FIG. 11B) may be formed by a patterning process using a deposition and etching process, and the bit lines 64b may be formed by a damascene process in which a conductive material is filled in the trenches (63 in FIG. 11D), as described with reference to FIG. 11D. Accordingly, the conductive shielding lines (57a, 57b, 57c, and 157 in FIGS. 1 to 9B) may be formed to have a predetermined height, thereby improving a variation in height of the conductive shielding lines (57a, 57b, 57c, and 157 in FIGS. 1 to 9B). The bit lines (64a, 64b, 64c, 64d, and 64e in FIGS. 1 to 9B) may be formed by a damascene process, thereby improving interface properties between channel structures (73 in FIG. 2B) in contact with the bit lines (64a, 64b, 64c, 64d, and 64e in FIGS. 1 to 9B) and the bit lines (64a, 64b, 64c, 64d, and 64e in FIGS. 1 to 9B). Accordingly, the semiconductor device 1 according to example embodiments may include patterned conductive shielding lines (57a, 57b, 57c, and 157 in FIGS. 1 to 9B) and bit lines (64a, 64b, 64c, 64d, and 64e in FIGS. 1 to 9B) having a damascene structure, thereby improving electrical performance and reliability.

According to example embodiments of the present disclosure, a semiconductor device including conductive shielding lines and bit lines being alternately arranged may be provided. The conductive shielding lines may serve to screen capacitive coupling between the bit lines. Accordingly, the conductive shielding lines may reduce or block parasitic capacitance between the bit lines, thereby minimizing RC delay of the bit lines.

The conductive shielding lines may be formed in a patterning process using a deposition and etching process. In some implementations, the bit lines may be formed in a damascene process in which a conductive material is filled in the trenches. Accordingly, the conductive shielding lines may be formed to have a predetermined height, thereby avoiding a variation in height of the conductive shielding lines. The bit lines may be formed in a damascene process, thereby improving interface properties between channel structures in contact with the bit lines and the bit lines. Accordingly, a semiconductor device according to example embodiments may include patterned conductive shielding lines and bit lines having a damascene structure, and thus may have improved electrical performance and reliability.

The various and beneficial advantages and effects of the present disclosure are not limited to the above description, and will be more easily understood in the course of describing specific example embodiments of the present disclosure.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

1. A semiconductor device comprising: a lower structure;an interlayer insulating layer on the lower structure;a conductive shielding line on the lower structure, the conductive shielding line penetrating through the interlayer insulating layer;a capping insulating layer on the interlayer insulating layer and the conductive shielding line; anda bit line on the lower structure and penetrating through the capping insulating layer and the interlayer insulating layer,wherein:an upper surface of the bit line is at a higher level than an upper surface of the conductive shielding line, anda lower surface of the bit line is at a level equal to or lower than a level of a lower surface of the conductive shielding line.

2. The semiconductor device as claimed in claim 1, wherein the bit line includes a conductive pattern and a barrier layer covering a side surface and a lower surface of the conductive pattern.

3. The semiconductor device as claimed in claim 1, wherein a slope of a side surface of the bit line is different from a slope of a side surface of the conductive shielding line.

4. The semiconductor device as claimed in claim 3, wherein the side surface of the bit line has a negative slope.

5. The semiconductor device as claimed in claim 3, wherein the side surface of the conductive shielding line has a positive slope.

6. The semiconductor device as claimed in claim 1, wherein: the conductive shielding line includes a shield barrier layer and a shield conductive pattern on the shield barrier layer,a thickness of the shield conductive pattern is greater than a thickness of the shield barrier layer, anda side surface of the shield conductive pattern is in contact with the interlayer insulating layer.

7. The semiconductor device as claimed in claim 1, wherein: the lower structure includes a first contact plug,the bit line is in contact with the first contact plug, anda width of the bit line is greater than a width of the first contact plug.

8. The semiconductor device as claimed in claim 7, wherein the bit line is in contact with an upper surface of the first contact plug and a side surface of an upper region of the first contact plug.

9. The semiconductor device as claimed in claim 7, wherein a lower surface of the bit line contacting the first contact plug has a downwardly curved shape.

10. The semiconductor device as claimed in claim 1, wherein a lowermost end of the bit line is at a lower level than a lowermost end of the conductive shielding line.

11. The semiconductor device as claimed in claim 1, further comprising: a vertical channel portion on the bit line;a word line facing a side surface of the vertical channel portion; anda dielectric structure between the side surface of the vertical channel portion and the word line.

12. The semiconductor device as claimed in claim 11, further comprising: a landing pad on the vertical channel portion; anda data storage structure on the landing pad.

13. The semiconductor device as claimed in claim 1, wherein the lower structure includes: a substrate;a peripheral circuit on the substrate; anda wiring structure electrically connected to the peripheral circuit on the substrate,wherein the wiring structure includes a first contact plug electrically connected to the bit line and a second contact plug electrically connected to the conductive shielding line.

14. The semiconductor device as claimed in claim 1, wherein the capping insulating layer includes a material different from a material of the interlayer insulating layer.

15. A semiconductor device comprising: a lower structure;a first conductive line on the lower structure; anda second conductive line on the lower structure, the second conductive line being spaced apart from the first conductive line,wherein an upper surface of the second conductive line is at a higher level than an upper surface of the first conductive line,wherein a lower surface of the second conductive line is at a level the same as or lower than a level of a lower surface of the first conductive line, andwherein a slope of a side surface of the second conductive line is different from a slope of a side surface of the first conductive line.

16. The semiconductor device as claimed in claim 15, wherein the second conductive line includes a conductive pattern and a barrier layer covering a side surface and a bottom surface of the conductive pattern.

17. The semiconductor device as claimed in claim 15, wherein: the side surface of the second conductive line has a negative slope,the side surface of the first conductive line is substantially vertical or has a positive slope.

18. A semiconductor device comprising: a substrate;a circuit device on the substrate;a wiring structure on the substrate and electrically connected to the circuit device;bit lines respectively extending in a first horizontal direction, and at a level higher than level of the wiring structure;conductive shielding lines arranged alternately with the bit lines in a second horizontal direction perpendicular to the first horizontal direction; andword lines respectively extending in the second horizontal direction, wherein the word lines are at a higher level than the bit lines and the conductive shielding lines,wherein upper surfaces of the bit lines are at a higher level than upper surfaces of the conductive shielding lines, andwherein each of the bit lines has a negative slope.

19. The semiconductor device as claimed in claim 18, wherein a lowermost end of each of the bit lines is at a lower level than a lowermost end of each of the conductive shielding lines.

20. The semiconductor device as claimed in claim 18, wherein a width of each of the bit lines is greater than a width of each of the conductive shielding lines.