Patent Application
20240178307
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0160792, filed on Nov. 25, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to a semiconductor device including a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device.
A transistor is a semiconductor device performing electrical switching, and is widely used in various semiconductor products such as a memory, a driving integrated circuit (IC), etc. When the size of a semiconductor device is reduced, the number of semiconductor devices that may be integrated in one wafer increases and a driving speed of the semiconductor device also increases. Thus, research on reducing the size of semiconductor devices has been actively conducted.
Recently, research on using two-dimensional (2D) materials has been conducted to reduce the size of semiconductor devices. A 2D material is stabilized and has excellent characteristics even with a thickness of 1 nm or less, and thus, has been highlighted as a material for overcoming limitations of performance degradation caused due to the reduction in the size of semiconductor devices.
A transistor structure used in semiconductor devices has developed from a sheet-type to a gate all around (GAA) structure through a fin field effect transistor (FINFET) structure. A multi-bridge channels (MBC)-FET that is a type of GAA structure that has just been introduced copes with degradation due to a short channel effect according to an increase in integration of semiconductor devices, through a structure in which plate-type thin channels are vertically stacked.
Provided is a semiconductor device including a multi-layer gate dielectric layer and an electronic apparatus including the semiconductor device.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to an embodiment, a semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a gate dielectric layer on a first area of the channel layer, a gate electrode on the gate dielectric layer, and a source electrode and a drain electrode in a second area of the channel layer. The gate dielectric layer may include a high-k dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer may be between the high-k dielectric layer and the channel layer. A dielectric constant of the intermediate layer may be less than a dielectric constant of the high-k dielectric layer.
In some embodiments, the intermediate dielectric layer may include a material having a dielectric constant of 9 or less.
In some embodiments, a thickness of the intermediate dielectric layer may be about 0.5 nm to about 2 nm.
In some embodiments, the intermediate dielectric layer may include at least one of C, Si, B, N, O, and Al.
In some embodiments, the intermediate dielectric layer may include a crystalline material.
In some embodiments, the intermediate dielectric layer may include grains having smaller sizes than grains of the 2D semiconductor material of the channel layer.
In some embodiments, the intermediate dielectric layer may include a crystalline material having a grain size of 50 nm or less.
In some embodiments, the intermediate dielectric layer may include an amorphous material.
In some embodiments, the intermediate dielectric layer may include a 2D material.
In some embodiments, the 2D semiconductor material of the channel layer may include one to ten layers.
In some embodiments, the 2D semiconductor material of the channel layer may include one to five layers.
In some embodiments, the 2D semiconductor material of the channel layer may have a material having a band-gap of about 0.1 eV to about 3.0 eV.
In some embodiments, the 2D semiconductor material may include transition metal dichalcogenide (TMD), black phosphorous, or graphene.
In some embodiments, the TMD may include a metal element and a chalcogen element. The metal element may include one of Mo, W, Nb, Sn, V, Ta, Ti, Zr, Hf, Tc, and Re, and the chalcogen element may include one of S, Se, and Te.
In some embodiments, the TMD may include at least one of MoS2, WS2, TaS2, HfS2, ReS2, TiS2, NbS2, SnS2, MoSe2, WSe2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, MoTe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, and SnTe2.
In some embodiments, the semiconductor device may further include a ferroelectric layer between the high-k dielectric layer and the intermediate dielectric layer.
In some embodiments, the ferroelectric layer may include at least one of an oxide ferroelectric material, a polymer ferroelectric material, and a fluoride ferroelectric material.
In some embodiments, the gate electrode may include metal, conductive nitride, or conductive oxide.
In some embodiments, the source electrode and the drain electrode may include a metal material.
According to an embodiment, an electronic apparatus includes any one of the above-described semiconductor devices.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., +10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., +10%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.
Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to accompanying drawings. In the drawings, like reference numerals denote like components, and sizes of components in the drawings may be exaggerated for convenience of explanation. The embodiments of the disclosure are capable of various modifications and may be embodied in many different forms.
When a layer, a film, a region, or a panel is referred to as being “on” another element, it may be directly on/under/at left/right sides of the other layer or substrate, or intervening layers may also be present. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. It will be further understood that when a portion is referred to as “comprising” another component, the portion may not exclude another component but may further comprise another component unless the context states otherwise.
The use of the term of “the above-described” and similar indicative terms may correspond to both the singular forms and the plural forms. Also, the steps of all methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.
Also, the terms “ . . . unit”, “ . . . module” used herein specify a unit for processing at least one function or operation, and this may be implemented with hardware or software or a combination of hardware and software.
Furthermore, the connecting lines or connectors shown in the drawings are intended to represent example functional relationships and/or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may be present in a practical device.
The use of any and all examples, or example language provided herein, is intended merely to better illuminate the disclosure and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.
The semiconductor device 100 of
Referring to
Referring to
The channel layer 120 according to the embodiment may include a two-dimensional (2D) semiconductor material. The 2D semiconductor material denotes a semiconductor material having a layered-structure in which element atoms are two-dimensionally bonded. The 2D semiconductor material has excellent electrical properties, and thus, characteristics thereof are not largely changed and high mobility of electrons may be maintained even when a thickness is reduced to a nano-scale.
The 2D semiconductor material may have a material having a band-gap of about 0.1 eV to about 3.0 eV. However, one or more embodiments are not limited thereto. The 2D semiconductor material may include, for example, transition metal dichalcogenide (TMD), black phosphorous, or graphene. However, one or more embodiments are not limited to the above example.
TMD is a compound of a transition metal and a chalcogen element. Here, the transition metal may include, for example, at least one selected from Mo, W, Nb, Sn, V, Ta, Ti, Zr, Hf, Tc, and Re, and the chalcogen element may include, for example, at least one selected from S, Se, and Te. In detail, the chalcogen element may include at least one selected from MoS2, WS2, TaS2, HfS2, ReS2, TiS2, NbS2, SnS2, MoSe2, WSe2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, MoTe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, and SnTe2. However, one or more embodiments are not limited to the above example.
The black phosphorous denotes a 2D material having a structure in which phosphor elements are two-dimensionally bonded. The graphene denotes a 2D material having a structure in which carbon (C) elements are two-dimensionally bonded.
The 2D semiconductor material forming the channel layer 120 may have a monolayer or a multilayer structure, and each layer may have a thickness in an atomic level. For example, the 2D semiconductor material may include one to ten layers. In more detail, for example, the 2D semiconductor material may include one to five layers. However, one or more embodiments are not limited thereto.
The channel layer 120 may include a certain dopant in order to adjust a mobility of the 2D semiconductor material. In detail, the 2D semiconductor material may be doped with a p-type dopant or an n-type dopant. The p-type dopant or the n-type dopant may be doped using an ion implantation or chemical doping method. However, one or more embodiments are not limited thereto.
A source of the p-type dopant may include, for example, ionic liquid such as NO2BF4, NOBF4, NO2SbF6, etc., acidic compound such as HCl, H2PO4, CH3COOH, H2SO4, HNO3, etc., an organic compound such as dichlorodicyanoquinone (DDQ), oxone, dimyristoylphosphatidylinositol (DMPI), trifluoromethanesulfoneimide, etc. Alternatively, the source of the p-type dopant may include HPtCl4, AuCl3, HAuCl4, silver trifluoromethanesulfonate (AgOTf), AgNO3, H2PdCl6, Pd(OAc)2, Cu(CN)2, etc.
A source of the n-type dopant may include, for example, a reduction product of a substituted or unsubstituted nicotinamide, a reduction product of a compound which is chemically bound to a substituted or unsubstituted nicotinamide, and a compound comprising at least two pyridinium moieties in which a nitrogen atom of at least one of the pyridinium moieties is reduced. For example, the source of the n-type dopant may include nicotinamide mononucleotide-H (NMNH), nicotinamide adenine dinucleotide-H (NADH), nicotinamide adenine dinucleotide phosphate-H (NADPH), or viologen. Alternatively, the source of the n-type dopant may include a polymer such as polyethylenimine (PEI), etc. Alternatively, the n-type dopant may include an alkali metal such as K, Li, etc. In addition, the p-type dopant and the n-type dopant materials mentioned above are examples, and the other various materials may be used as the dopant.
The gate dielectric layer 130 is provided in the first area of the channel layer 120, such as on the first area of the channel layer 120, and a gate electrode 140 is provided on the gate dielectric layer 130. The gate dielectric layer 130 may include, for example, silicon nitride, etc., but is not limited thereto. The gate electrode 140 may include metal, conductive nitride, or conductive oxide. Here, the metal may include, for example, at least one from Au, Ti, W, Mo, Pt, and Ni. The conductive nitride may include, for example, TiN, TaN, WN, etc., and the conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, one or more embodiments are not limited to the above examples.
The source electrode and the drain electrode may be provided in the second area of the channel layer 120, such as one the second area of the channel layer 120. The source electrode and the drain electrode may include, but are not limited to, a metal material.
The gate dielectric layer 130 may include the high-k dielectric layer 131 and the intermediate dielectric layer 132. The intermediate dielectric layer 132 denotes a dielectric layer that is provided between the high-k dielectric layer 131 and the channel layer 120 and has a less dielectric constant than that of the high-k dielectric layer 131.
According to the semiconductor device according to the related art, there is an issue of reducing or deteriorating a mobility of a channel layer due to occurrence of a remote phonon scattering effect although a capacitance of the gate dielectric layer increases as a dielectric constant of a material included in the gate dielectric layer increases. On the contrary, as the dielectric constant of the material included in the gate dielectric layer decreases, the remote phonon scattering effect is reduced, but a gate capacitance degrades and the channel mobility may also decrease. To address the above issue, an intermediate dielectric layer having a relatively small dielectric constant is inserted in the high-k dielectric layer, thereby reducing the remote phonon scattering effect and the channel mobility degradation. This will be described in detail later.
The intermediate dielectric layer 132 may be disposed between the channel layer 120 including the 2D semiconductor material and the high-k dielectric layer 131 may include a material having a dielectric constant of 9 or less. In contrast, the high-k dielectric layer 131 may include a material having a dielectric constant greater than 9.
The thickness of the intermediate dielectric layer 132 may be about 0.5 nm to about 2 nm. The thickness of the intermediate dielectric layer 132 may be less than that of the high-k dielectric layer 131. However, one or more embodiments are not limited thereto.
Because the thickness of the intermediate dielectric layer 132 is less than that of the high-k dielectric layer 131, the remote phonon scattering effect or a charged impurity scattering effect may be lessened, and accordingly, the mobility of the channel layer may be improved.
The intermediate dielectric layer 132 may include at least one selected from C, Si, B, N, O, and Al. However, one or more embodiments are not limited thereto.
The intermediate dielectric layer 132 may include a crystalline material. The crystalline material denotes a structure having grains, and each grain may have a grain size.
The intermediate dielectric layer 132 may include a 2D material, and the 2D material may include a 2D semiconductor material. The 2D semiconductor material may include, for example, TMD, black phosphorous, or graphene. However, one or more embodiments are not limited to the above example. However, one or more embodiments are not limited thereto.
The 2D semiconductor material of the channel layer 120 may have grains, and the 2D material of the intermediate dielectric layer 132 may include grains having a grain size less than the 2D semiconductor material of the channel layer 120. In detail, the 2D material of the intermediate dielectric layer 132 may include a crystalline material having a grain size of 50 nm or less.
When the 2D material of the intermediate dielectric layer 132 has the grains having a smaller grain size than that of the 2D semiconductor material of the channel layer 120, a surface roughness scattering effect may be lessened, and uniform deposition of the high-k dielectric layer 131 disposed on the intermediate dielectric layer 132 may be easily carried out. When the high-k dielectric layer 131 is uniformly deposited, the channel mobility may be improved and leakage current from the gate may be limited and/or prevented.
In some embodiments, the intermediate dielectric layer 132 may include one or more low-k materials. The intermediate dielectric layer 132 may include SiO2 or SiNx. The intermediate dielectric layer 132 may include one or more 2D low-k materials, such as h-BN and a-BN.
Referring to
When
The intermediate dielectric layer may include an amorphous material.
An amorphous material refers to a phase having a uniform composition, but being in a state where atomic arrangement is disordered, not in a regular lattice form, and may include a material in that phase.
When the intermediate dielectric layer includes the amorphous material, the dielectric material layer may not include grains.
Referring to
Referring to
The 2D semiconductor material in the channel layer 120 may have a single-layered or multi-layered structure. For example, the 2D semiconductor material may have, but is not limited to, one to ten layers (for example, one to five layers). The channel layer 520 may further include a certain dopant such as a p-type dopant or an n-type dopant.
A gate dielectric layer 230 is provided on the channel layer 120, and a gate electrode 140 is provided on the gate dielectric layer 230. The gate dielectric layer 230 may include the high-k dielectric layer 231, an intermediate dielectric layer 232, and the ferroelectric layer 233.
The ferroelectric layer 233 may be disposed between the high-k dielectric layer 231 and the intermediate dielectric layer 232, but is not limited thereto. The ferroelectric layer 233 may be arranged parallel to the high-k dielectric layer or parallel to the intermediate dielectric layer, but is not limited thereto.
The ferroelectric layer 233 may include at least one selected from an oxide ferroelectric material, a polymer ferroelectric material, a fluoride ferroelectric material, but is not limited thereto.
Referring to
As technology has developed, a semiconductor device has developed from a sheet-type to a gate all around (GAA) structure through a fin field effect transistor (FINFET) structure in order to manufacture high-integration transistor. A multi-bridge channel (MBC) FET is a kind of GAA transistor structure and denotes a structure in which a plurality of plate-shaped thin channel layers are vertically stacked. A structure in which four surfaces of the plurality of plate-shaped channel layers are surrounded by the gate electrode is referred to as the MBC FET structure.
Referring to
A gate dielectric layer (not shown) is provided, and the gate electrode 140 is provided on the gate dielectric layer (not shown). Here, the gate dielectric layer (not shown) is provided to surround four surfaces of the channel layers 120, and the gate electrode 140 may be provided to surround four surfaces of the gate dielectric layer (not shown). Although not shown in the drawings, the source and drain electrodes may be provided at left and right sides of the channel layer 120.
Referring to
The gate dielectric layer 430 may include a high-k dielectric layer 431 and an intermediate dielectric layer 432, and may further include an oxide dipole layer, a TiN barrier layer, and a work function material. However, one or more embodiments are not limited thereto.
The above-described semiconductor devices 100, 200, 300, and 400 may be applied to a memory device, for example, a DRAM device. The memory device may have a structure in which the semiconductor devices 100, 200, 300, or 400 and a capacitor are electrically connected to each other. For example,
Referring to
In detail, the memory unit 1010, the ALU 1020, and the control unit 1030 may be connected to one another via metal lines on-chip and directly communicate with one another. The memory unit 1010, the ALU 1020, and the control unit 1030 may be monolithically integrated on one substrate and form one chip. An input/output device 2000 (e.g., keyboard, display, mouse) may be connected to the electronic device architecture (chip) 1000.
The ALU 1020 and the control unit 1030 may independently include the semiconductor devices 100-400 described above, and the memory unit 1010 may include the semiconductor devices 100, 200, 300, and 400, a capacitor, or combinations thereof (e.g., memory devices 101, 201, 401). The memory unit 1010 may include a main memory and a cache memory. The electronic device architecture (chip) 1000 may be an on-chip memory processing unit.
Referring to
In some cases, the electronic device architecture may be implemented in a form in which computing unit devices and memory unit devices are adjacent to each other in one chip, without distinction of sub-units. Although the embodiments have been described above, these are merely an example, and various modifications may be made therefrom by those of ordinary skill in the art.
The semiconductor device according to the embodiment includes the channel layer including the 2D semiconductor material, the gate dielectric layer provided in the first area of the channel layer, the gate electrode provided on the gate dielectric layer, and the source and drain electrodes provided in the second area of the channel layer, and the gate dielectric layer includes the high-k dielectric layer, and the intermediate dielectric layer provided between the high-k dielectric layer and the channel layer and having a less dielectric constant than that of the high-k dielectric layer. The intermediate dielectric layer provided between the high-k dielectric layer and the channel layer may limit and/or prevent the remote phonon scattering effect and the reduction in the channel mobility, and because the grain size of the 2D material in the intermediate dielectric layer is less than the grain side of the 2D semiconductor material in the channel layer, the uniform deposition of the high-k dielectric layer may be carried out.
The CPU 1500 may read and write data from and into the main memory 1600 in response to read and write requests of a host 1800. The CPU 1500 may make an address mapping table for mapping an address provided from the host 1800 (e.g., a mobile device or a computer system) into a physical address of the main memory 1600. The main memory 1600 may include a plurality of memory cells MC. Each of the memory cells MC and include a data storage (e.g., capacitor C) connected to a transistor TR and may have a structure including any one of the semiconductor devices 100, 200, 300, and 400, and/or memory devices 101, 201, and 401. The transistor TR may be provided at an intersection between a bit line BL and word line WL.
However, effects of the present disclosure are not limited to the above disclosure.
One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0160792 | Nov 2022 | KR | national |
