SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF FABRICATING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0090616, filed on Jul. 21, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND
1. Field

The present disclosure relates to semiconductor devices including a two-dimensional material and methods of fabricating the semiconductor devices.

2. Description of the Related Art

Transistors are semiconductor devices having an electrical switching function and are used in various semiconductor products such as memories and driving integrated circuits (ICs). A decrease in the size of semiconductor devices may have an effect of increasing the number of semiconductor devices integrated on one wafer and increasing the driving speed of semiconductor devices. Thus, much research has been conducted to reduce the size of semiconductor devices.

Recently, methods of reducing the size of semiconductor devices by using two-dimensional materials have been researched. Two-dimensional materials have stable and good characteristics even when having a small thickness within the range of about 1 nm or less, and thus there is interest in two-dimensional materials for addressing a decrease in the performance of semiconductor devices caused by a decrease in the size of semiconductor devices.

SUMMARY

Provided are semiconductor devices including a two-dimensional material and methods of fabricating the semiconductor devices.

Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

According to an embodiment, a semiconductor device may include at least one first two-dimensional material layer; a source electrode and a drain electrode that are respectively on both sides of the at least one first two-dimensional material layer; second two-dimensional material layers respectively on a side of the source electrode and a side of the drain electrode and connected to the at least one first two-dimensional material layer; a gate insulating layer surrounding the at least one first two-dimensional material layer; and a gate electrode on the gate insulating layer.

In some embodiments, the second two-dimensional material layers may extend in a direction substantially perpendicular to the at least one first two-dimensional material layer.

In some embodiments, the second two-dimensional material layers may be in planar contact with the source electrode and the drain electrode.

In some embodiments, the at least one first two-dimensional material layer may include a plurality of first two-dimensional material layers. The plurality of first two-dimensional material layers may extend in a direction substantially perpendicular to the second two-dimensional material layers, and the plurality of first two-dimensional material layers may be spaced apart from each other. All or some of the plurality of first two-dimensional material layers may be connected to the second two-dimensional material layers.

In some embodiments, the at least one first two-dimensional material layer may include a transition metal dichalcogenide (TMD) or black phosphorus. The TMD may include at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re. The chalcogen element may include at least one of S, Se, and Te.

In some embodiments, the second two-dimensional material layers may include a two-dimensional material having semiconductor characteristics, metallic characteristics, or semi-metallic characteristics. The second two-dimensional material layers may include a TMD, black phosphorus, or graphene.

In some embodiments, the at least one first two-dimensional material layer and the second two-dimensional material layers may each independently include one to ten layers. The at least one first two-dimensional material layer and the second two-dimensional material layers may each independently include one to five layers.

In some embodiments, a number of the second two-dimensional material layers may be greater than or equal to a number of at least one first two-dimensional material layer.

In some embodiments, the at least one first two-dimensional material layer, the second two-dimensional material layers, or both the at least one first two-dimensional material layer and the second two-dimensional material layers may include a dopant.

According to an embodiment, an electronic apparatus may include the semiconductor device.

According to an embodiment, a method of fabricating a semiconductor device may include alternately stacking at least one sacrificial layer and at least one first two-dimensional material layer on a substrate; etching a first side and a second side of the at least one first two-dimensional material layer and the at least one sacrificial layer in a first direction to provide a first etched side and a second etched side of the at least one first two-dimensional material layer and the at least one first sacrificial layer; forming second two-dimensional material layers respectively on both the first etched side and the second etched side of the at least one first two-dimensional material layer and the at least one first sacrificial layer; forming a source electrode and a drain electrode respectively on the first etched side and the second etched side of the at least one first two-dimensional material layer and the at least one first sacrificial layer such that the source electrode and the drain electrode are in contact with the second two-dimensional material layers; removing the at least one sacrificial layer and then forming a gate insulating layer that surrounds the at least one first two-dimensional material layer; and forming a gate electrode on the gate insulating layer.

In some embodiments, the method may further include etching, in a second direction perpendicular to the first direction, a third side and a fourth side of the at least one first two-dimensional material layer and the at least one sacrificial layer after the etching the first side and the second side of the at least one first two-dimensional material layer and the at least one first sacrificial layer in the first direction is performed.

In some embodiments, the forming the second two-dimensional material layers may include growing the second two-dimensional material layers on edge portions of the at least one first two-dimensional material layer in a direction substantially perpendicular to the at least one first two-dimensional material layer.

In some embodiments, the at least one first two-dimensional material layer may include a plurality of first two-dimensional material layers, and the forming the second two-dimensional material layers may include forming the second two-dimensional material layers connected to all or some of the plurality of first two-dimensional material layers.

In some embodiments, the second two-dimensional material layers may be in planar contact with the source electrode and the drain electrode.

In some embodiments, the at least one first two-dimensional material layer may include a two-dimensional material having semiconductor characteristics. The at least one first two-dimensional material layer may include a material having a bandgap of about 0.1 eV to about 3.0 eV. The at least one first two-dimensional material layer may include a transition metal dichalcogenide (TMD) or black phosphorus.

In some embodiments, the at least one first two-dimensional material layer and the second two-dimensional material layers may each independently include one to ten layers.

In some embodiments, a number of layers in the second two-dimensional material layers may be greater than or equal to a number of layers in the at least one first two-dimensional material layer.

In some embodiments, the at least one first two-dimensional material layer, the second two-dimensional material layer, or both the at least one first two-dimensional material layer and the second two-dimensional material layer may include a dopant.

According to an embodiment, a semiconductor device may include a substrate; a source electrode and a drain electrode spaced apart from each other in a first direction on a surface of the substrate; a channel structure between the source electrode and the drain electrode, the channel structure including a first two-dimensional material layer extending in the first direction between a surface of the source electrode and a surface of the drain electrode; a gate insulating layer surrounding the channel structure; a gate electrode on the gate insulating layer, the gate electrode being spaced apart from the source electrode and the drain electrode; and a plurality of second two-dimensional material layers spaced apart from each other on the substrate. A first pair of the plurality of second two-dimensional material layers respectively may contact opposite sides of the first two-dimensional material layer and respectively extend along the surface of the source electrode and the surface of the drain electrode.

In some embodiments, the first pair of the second two-dimensional material layers may be in planar contact with the source electrode and the drain electrode.

In some embodiments, the first two-dimensional material layer may include a transition metal dichalcogenide (TMD) or black phosphorus, and the plurality of second two-dimensional material layers may include a TMD, black phosphorus, or graphene.

In some embodiments, the channel structure may include a plurality of first two-dimensional material layers spaced apart from each other over the surface of the substrate. The plurality of first two-dimensional material layers may extend in the first direction between the surface of the source electrode and the surface of the drain electrode. The first pair of the plurality of second two-dimensional material layers respectively may contact opposite sides of each of the plurality of first two-dimensional material layers.

In some embodiments, the channel structure may include an additional first two-dimensional material layer spaced apart from the first two-dimensional material layer over the surface of the substrate. The additional first two-dimensional material layer may extend in the first direction between the surface of the source electrode and the surface of the drain electrode. A second pair of the plurality of second two-dimensional material layers respectively may contact opposite sides of the additional first two-dimensional material layer and respectively extend along the surface of the source electrode and the surface of the drain electrode. The first pair of the plurality of second two-dimensional material layers and the second pair of the plurality of second two-dimensional material layers may be spaced apart from each other over the surface of the substrate.

According to an embodiment, an electronic apparatus may include the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a perspective view illustrating a semiconductor device according to an example embodiment;

FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1;

FIG. 3 is a cross-sectional view illustrating a semiconductor device according to another example embodiment;

FIGS. 4A to 10C are views illustrating a method of fabricating a semiconductor device according to example embodiments;

FIGS. 11 and 12 are conceptual views schematically illustrating device architectures applicable to electronic apparatuses according to example embodiments.

FIG. 13 is a block diagram of an electronic apparatus according to an embodiment; and

FIG. 14 is a schematic block diagram of a display apparatus according to an embodiment.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be construed as A only, B only, C only, or any combination of two or more of A, B, and C, such as, for instance, ABC, AB, BC, and AC.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.

Hereinafter, example embodiments will be described with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and the sizes of elements may be exaggerated for clarity of illustration. The embodiments described herein are for illustrative purposes only, and various modifications may be made therein.

In the following description, when an element is referred to as being “above” or “on” another element, it may be directly on an upper, lower, left, or right side of the other element while making contact with the other element or may be above an upper, lower, left, or right side of the other element without making contact with the other element. The terms of a singular form may include plural forms unless otherwise mentioned. It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

An element referred to with the definite article or a demonstrative determiner may be construed as the element or the elements even though it has a singular form. Operations of a method may be performed in an appropriate order unless explicitly described in terms of order or described to the contrary, and are not limited to the stated order thereof.

In the present disclosure, terms such as “unit” or “module” may be used to denote a unit that has at least one function or operation and is implemented with hardware, software, or a combination of hardware and software.

Furthermore, line connections or connection members between elements depicted in the drawings represent functional connections and/or physical or circuit connections by way of example, and in actual applications, they may be replaced or embodied with various additional functional connections, physical connections, or circuit connections.

Examples or example terms are just used herein to describe technical ideas and should not be considered for purposes of limitation unless defined by the claims.

FIG. 1 is a perspective view illustrating a semiconductor device 100 according to an example embodiment. The semiconductor device 100 illustrated in FIG. 1 may be, for example, a multi bridge channel field effect transistor (MBC-FET). FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1.

Referring to FIGS. 1 and 2, a channel layer is provided on a substrate 110. The substrate 110 may include various materials. For example, the substrate 110 may include a semiconductor (e.g., single crystal silicon) substrate, a compound semiconductor substrate, or a semiconductor-on-insulator (SOI) substrate. However, the listed substrates are merely examples. In addition, the substrate 110 may further include, for example, an impurity region formed by doping, an electronic device such as a transistor, or a peripheral circuit configured to select and control memory cells for storing data.

The channel layer includes one or more first two-dimensional material layers 120 stacked in a direction substantially perpendicular to the substrate 110 (for example, a z-axis direction). Here, each of the first two-dimensional material layers 120 may extend in a direction parallel to the substrate 110. FIGS. 1 and 2 illustrate an example in which four first two-dimensional material layers 120 are stacked at a distance from each other in the direction perpendicular to the substrate 110. Here, the first two-dimensional material layers 120 may form a multi-bridge channel. However, this is merely an example, and in another example, the channel layer may include one first two-dimensional material layer 120. Hereinafter, the case in which the channel layer includes a plurality of first two-dimensional material layers 120 will be described as an example.

The first two-dimensional material layers 120 may include a two-dimensional material having semiconductor characteristics. The two-dimensional material refers to a material having a layered structure in which constituent atoms are two-dimensionally bonded to each other. The two-dimensional material having semiconductor characteristics may have good electrical characteristics, and even when having a nanoscale thickness, the two-dimensional material may maintain high mobility without significant changes in the characteristics thereof.

The first two-dimensional material layers 120 may include a material having a bandgap of about 0.1 eV to about 3.0 eV. For example, the first two-dimensional material layers 120 may include a transition metal dichalcogenide (TMD) or black phosphorus. However, the first two-dimensional material layers 120 are not limited thereto.

The TMD is a two-dimensional material, which has semiconductor characteristics and is a compound of a transition metal and a chalcogen element. Here, the transition metal may include, for example, at least one selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Co, Tc, and Re, and the chalcogen element may include, for example, at least one selected from the group consisting of S, Se, and Te. Examples of the TMD may include MoS₂, MoSe₂, MoTe₂, WS₂, WSe₂, WTe₂, ZrS₂, ZrSe₂, HfS₂, HfSe₂, NbSe₂, ReSe₂, and the like. However, examples of the TMD are not limited thereto. The black phosphorus is a semiconductor material having a structure in which phosphorus (P) atoms are two-dimensionally bonded to each other.

The first two-dimensional material layers 120 may further include a dopant to control mobility. The first two-dimensional material layers 120 may be doped with a p-type dopant or an n-type dopant. The first two-dimensional material layers 120 may be doped with the p-type dopant or the n-type dopant by an ion implantation method or a chemical doping method.

For example, a source of the p-type dopant may include: an ionic liquid such as NO₂BF₄, NOBF₄, or NO₂SbF₆; an acid compound such as HCl, H₂PO₄, CH₃COOH, H₂SO₄, or HNO₃; an organic compound such as dichlorodicyanoquinone (DDQ), oxone, dimyristoylphosphatidylinositol (DMPI), or trifluoromethanesulfoneimide; or the like. Alternatively, the source of the p-type dopant may include HPtCl₄, AuCl₃, HAuCl₄, silver trifluoromethanesulfonate (AgOTf), AgNO₃, H₂PdCl₆, Pd(OAc)₂, Cu(CN)₂, or the like.

Examples of a source of the n-type dopant may include: a reduction product of a substituted or unsubstituted nicotinamide; a reduction product of a compound which is chemically bound to a substituted or unsubstituted nicotinamide; and a compound including at least two pyridinium moieties in which a nitrogen atom of at least one of the pyridinium moieties is reduced. For example, the source of the n-type dopant may include nicotinamide mononucleotide-H (NMNH), nicotinamide adenine dinucleotide-H (NADH), nicotinamide adenine dinucleotide phosphate-H (NADPH), or viologen. Alternatively, the source of the n-type dopant may include a polymer such as polyethylenimine (PEI). Alternatively, the n-type dopant may include an alkali metal such as K or Li. The materials listed above as p-type dopant materials or n-type dopant materials are merely examples, and other various materials may be used as dopants.

Each of the first two-dimensional material layers 120 may have a monolayer or multilayer structure in which each layer has an atomic level thickness. Each of the first two-dimensional material layers 120 may include, for example, one to ten layers. For example, each of the first two-dimensional material layers 120 may include one to five layers. However, the first two-dimensional material layers 120 are not limited thereto.

A source electrode 141 and a drain electrode 142 are respectively provided on both sides of the channel layer which includes the first two-dimensional material layers 120. The source electrode 141 and the drain electrode 142 may include, for example, a metal material having high electrical conductivity, such as Ag, Au, Pt, or Cu, but are not limited thereto.

Both ends of the channel layer including the first two-dimensional material layers 120 are electrically connected to a pair of second two-dimensional material layers 131 and 132. Here, each of the second two-dimensional material layers 131 and 132 may extend in a direction substantially perpendicular to the first two-dimensional material layers 120, that is, in the direction (for example, the z-axis direction) substantially perpendicular to the substrate 110. The second two-dimensional material layers 131 and 132 may be respectively provided on one side of the source electrode 141 and one side of the drain electrode 142.

The second two-dimensional material layer 131 provided on one side of the source electrode 141 may be electrically connected to end portions of the first two-dimensional material layers 120. The second two-dimensional material layer 132 provided on one side of the drain electrode 142 may be electrically connected to the other end portions of the first two-dimensional material layers 120. Here, all of the first two-dimensional material layers 120 may be electrically connected to each of the second two-dimensional material layers 131 and 132.

Each of the second two-dimensional material layers 131 and 132 may be in planar contact with the source electrode 141 and the drain electrode 142, and thus the contact resistance between the second two-dimensional material layers 131 and 132 and the source and drain electrodes 141 and 142 may be reduced.

The second two-dimensional material layers 131 and 132 may include a two-dimensional material having semiconductor characteristics, metallic characteristics, or semi-metallic characteristics. For example, the second two-dimensional material layers 131 and 132 may include a TMD or black phosphorus. The TMD may include a material, which has semiconductor characteristics or metallic characteristics depending on the crystal structure thereof. For example, the second two-dimensional material layers 131 and 132 may include a two-dimensional material having semi-metallic characteristics, such as graphene and antimony. For example, the second two-dimensional material layers 131 and 132 may include the same material as that included in the first two-dimensional material layers 120. However, embodiments are not limited thereto, and in another example, the second two-dimensional material layers 131 and 132 may include a material different from a material included in the first two-dimensional material layers 120. The second two-dimensional material layers 131 and 132 may further include a dopant to further reduce contact resistance.

Each of the second two-dimensional material layers 131 and 132 may have a monolayer or multilayer structure in which each layer has an atomic level thickness. Each of the second two-dimensional material layers 131 and 132 may include, for example, one to ten layers. For example, each of the second two-dimensional material layers 131 and 132 may include one to five layers. However, embodiments are not limited thereto. The number of layers included in each of the second two-dimensional material layers 131 and 132 may be equal to or greater than the number of layers included in each of the first two-dimensional material layers 120. The second two-dimensional material layers 131 and 132 may each include a plurality of layers to reduce contact resistance with the source and drain electrodes 141 and 142.

The second two-dimensional material layers 131 and 132 may be grown through edge epitaxy on the end portions of the first two-dimensional material layers 120. As a result, the contact resistance between the first two-dimensional material layers 120 and the second two-dimensional material layers 131 and 132 may be reduced.

A gate insulating layer 150 is provided to surround the first two-dimensional material layers 120 which forms the channel layer, and a gate electrode 160 is provided on the gate insulating layer 150.

The gate insulating layer 150 may include, for example, silicon nitride, but is not limited thereto. The gate electrode 160 may include a metal material or a conductive oxide. Here, the metal material may include, for example, at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. In addition, the conductive oxide may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like. However, the listed materials are merely examples.

The contact resistance of a planar contact between one surface of a two-dimensional semiconductor material and a metal material may be less than the contact resistance of an edge contact between an edge portion of the two-dimensional semiconductor material and the metal material. In addition, when a two-dimensional material having semi-metallic characteristics forms an edge contact, the contact resistance of the edge contact may increase because of, for example, a metal-induced gap state (MIGS) or a defect-induced gap state (DIGS). However, when the two-dimensional material having semi-metallic characteristics forms a planar contact, the contact resistance of the planar contact may be relatively low because the occurrence of an MIGS or DIGS reduces.

In the semiconductor device 100 of the current embodiment, the second two-dimensional material layers 131 and 132 electrically connected to the at least one first two-dimensional material layer 120 forming the channel layer are in planar contact with the source and drain electrodes 141 and 142, and thus the contact resistance between the second two-dimensional material layers 131 and 132 and the source and drain electrodes 141 and 142 may be reduced. In addition, because the second two-dimensional material layers 131 and 132 have a gating effect, the contact resistance between the second two-dimensional material layers 131 and 132 and the source and drain electrodes 141 and 142 may be further reduced when Schottky contact are formed between the second two-dimensional material layers 131 and 132 and the source and drain electrodes 141 and 142. Because the second two-dimensional material layers 131 and 132 are grown through edge epitaxy on the end portions of the first two-dimensional material layers 120, the contact resistance between the first two-dimensional material layers 120 and the second two-dimensional material layers 131 and 132 may also be reduced.

FIG. 3 is a cross-sectional view illustrating a semiconductor device 200 according to another example embodiment. Hereinafter, differences from the previous embodiment will be mainly described.

Referring to FIG. 3, a channel layer includes a plurality of first two-dimensional material layers 220 stacked in a direction (for example, a z-axis direction) substantially perpendicular to a substrate 110. FIG. 3 illustrates an example in which four first two-dimensional material layers 220 are stacked at a distance from each other in the direction perpendicular to the substrate 110. The descriptions of the first two-dimensional material layers 120 apply to the first two-dimensional material layers 220, and thus the first two-dimensional material layers 220 will not be described in detail here.

Both ends of the channel layer including the first two-dimensional material layers 220 are electrically connected to a pair of second two-dimensional material layers 231 and 232. Here, each of the second two-dimensional material layers 231 and 232 may be provided in a direction substantially perpendicular to the first two-dimensional material layer 220, that is, in the direction (for example, the z-axis direction) substantially perpendicular to the substrate 110. Because the first two-dimensional material layers 220 have been described above, detailed descriptions thereof will not be presented here.

In the current embodiment, each of the second two-dimensional material layers 231 and 232 may include a plurality of material layers, which are apart from each other. The material layers may be grown through edge epitaxy on end portions of the first two-dimensional material layers 220. Here, conditions for growing the material layers may be adjusted such that the material layers may be formed apart from each other instead of being formed in one piece.

Each of the material layers may be electrically connected to a portion of the first two-dimensional material layers 220. FIG. 3 illustrates an example in which one material layer is connected to one first two-dimensional material layer 220. However, embodiments are not limited thereto. In another example, two or three first two-dimensional material layers 220 may be connected to one material layer.

FIGS. 4A to 10C are views illustrating a method of fabricating a semiconductor device according to example embodiments. Among FIGS. 4A to 4C, FIG. 4B is a cross-sectional view taken along line B-B′ of FIG. 4A, and FIG. 4C is a cross-sectional view taken along line C-C′ of FIG. 4A. This applies to the following drawings.

Referring to FIGS. 4A to 4C, a stacked structure is formed by alternately depositing a plurality of first two-dimensional material layers 120 and a plurality of sacrificial layers 170 on an upper surface of a substrate 110. The substrate 110 may include various materials. For example, the substrate 110 may include a single crystal silicon substrate, a compound semiconductor substrate, or an SOI substrate. However, the listed substrates are merely examples. In addition, the substrate 110 may further include, for example, an impurity region formed by doping, an electronic device such as a transistor, or a peripheral circuit configured to select and control memory cells for storing data.

The first two-dimensional material layers 120 and the sacrificial layers 170 may be alternately deposited in a direction substantially perpendicular to the substrate 110 (for example, a z-axis direction). The first two-dimensional material layers 120 and the sacrificial layers 170 may be deposited by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). However, the listed deposition methods are merely examples.

The first two-dimensional material layers 120 include a two-dimensional material having semiconductor characteristics. The first two-dimensional material layers 120 may include a material having a bandgap of about 0.1 eV to about 3.0 eV. For example, the first two-dimensional material layers 120 may include a TMD or black phosphorus. However, the first two-dimensional material layers 120 are not limited thereto.

The sacrificial layers 170 formed between the first two-dimensional material layers 120 may include a material having etching selectivity with respect to the first two-dimensional material layers 120.

Referring to FIGS. 5A to 5C, both lateral portions of the stacked structure shown in FIG. 4A are etched in a first direction (for example, a y-axis direction), and then second two-dimensional material layers 131 and 132 are respectively deposited on both sides of the etched stacked structure. Therefore, each of the second two-dimensional material layers 131 and 132 may be formed in a direction substantially perpendicular to the first two-dimensional material layers 120.

For example, an etching mask (not shown) is formed using a photoresist on an upper surface of the stacked structure shown in FIG. 4A, and then both lateral portions of the stacked structure, which are exposed through the etching mask, are removed by etching. Next, the second two-dimensional material layers 131 and 132 are respectively deposited on both sides of the stacked structure.

The second two-dimensional material layers 131 and 132 may be deposited by, for example, CVD or ALD. In this deposition process, the second two-dimensional material layers 131 and 132 may be grown through edge epitaxy respectively on end portions of each of the first two-dimensional material layers 120. FIGS. 5A and 5B illustrate an example in which each of the second two-dimensional material layers 131 and 132 is formed in one piece. However, growth conditions may be adjusted such that each of the second two-dimensional material layers 131 and 132 may include a plurality of material layers that are apart from each other as shown in FIG. 3.

The second two-dimensional material layers 131 and 132 may include a two-dimensional material having semiconductor characteristics, metallic characteristics, or semi-metallic characteristics. For example, the second two-dimensional material layers 131 and 132 may include a TMD or black phosphorus. For example, the second two-dimensional material layers 131 and 132 may include graphene, antimony, or the like. The second two-dimensional material layers 131 and 132 may include the same material as that included in the first two-dimensional material layers 120. However, embodiments are not limited thereto, and the second two-dimensional material layers 131 and 132 may include a material different from that included in the first two-dimensional material layers 120. In addition, the second two-dimensional material layers 131 and 132 may be doped with a dopant.

Referring to FIGS. 6A to 6C, a source electrode 141 and a drain electrode 142 are respectively formed on both sides of the stacked structure of the first two-dimensional material layers 120 and the sacrificial layers 170. The source electrode 141 may be deposited on the second two-dimensional material layer 131 provided on one side of the stacked structure, and the drain electrode 142 may be deposited on the second two-dimensional material layer 132 provided on the other side of the stacked structure. Here, the second two-dimensional material layers 131 and 132 may be respectively in planar contact with the source and drain electrodes 141 and 142. The source electrode 141 and the drain electrode 142 may include, for example, a metal material having high electrical conductivity, such as Ag, Au, Pt, or Cu, but are not limited thereto.

Referring to FIGS. 7A to 7C, both sides of the stacked structure of the first two-dimensional material layers 120 and the sacrificial layers 170 are etched in a second direction (for example, an x-axis direction) perpendicular to the first direction. Referring to FIGS. 8A to 8C, the sacrificial layers 170 provided between the first two-dimensional material layers 120 are removed. Surfaces of the first two-dimensional material layers 120 may be exposed owing to the removal of the sacrificial layers 170.

Referring to FIGS. 9A to 9C, a gate insulating layer 150 is deposited to cover the exposed surfaces of the first two-dimensional material layers 120. The gate insulating layer 150 may surround the first two-dimensional material layers 120. The gate insulating layer 150 may include, for example, silicon nitride, but is not limited thereto.

Referring to FIGS. 10A to 10C, a gate electrode 160 is deposited on the gate insulating layer 150. The gate electrode 160 may surround the first two-dimensional material layers 120 which form a channel layer between the source electrode 141 and the drain electrode 142. The gate electrode 160 may include a metal material or a conductive oxide. Here, the metal material may include, for example, at least one selected from the group consisting of Au, Ti, TiN, TaN, W, Mo, WN, Pt, and Ni. In addition, the conductive oxide may include, for example, ITO, IZO, or the like. However, the listed materials are merely examples.

The semiconductor devices 100 and 200 described above may be applied to, for example, memory devices such as a DRAM device. The memory devices may have a structure in which the semiconductor device 100 or 200 described above is electrically connected to a capacitor. In addition, the semiconductor devices 100 and 200 may be applied to various electronic apparatuses. For example, the semiconductor devices 100 and 200 may be used for arithmetic operations, program execution, temporary data retention, or the like in electronic apparatuses such as mobile devices, computers, laptop computers, sensors, network devices, or neuromorphic devices.

FIGS. 11 and 12 are conceptual views schematically illustrating electronic device architectures applicable to electronic apparatuses according to example embodiments.

Referring to FIG. 11, an electronic device architecture 1000 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, the ALU 1020, and the control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1000 may be implemented as one chip including the memory unit 1010, the ALU 1020, and the control unit 1030.

For example, the memory unit 1010, the ALU 1020, and the control unit 1030 may be interconnected with each other on a chip through metal lines for direct communication with each other. The memory unit 1010, the ALU 1020, and the control unit 1030 may be monolithically integrated on a single substrate to form a single chip. Input/output devices 2000 may be connected to the electronic device architecture (chip) 1000.

The ALU 1020 and the control unit 1030 may each independently include the semiconductor devices 100 and 200 described above; and the memory unit 1010 may include the semiconductor devices 100 and 200 described above, capacitors, or combinations thereof. The memory unit 1010 may include both a main memory and a cache memory. The electronic device architecture (chip) 1000 may be an on-chip memory processing unit.

Referring to FIG. 12, a cache memory 1510, an ALU 1520, and a control unit 1530 may form a central processing unit (CPU) 1500. The cache memory 1510 may include a static random access memory (SRAM) including the semiconductor devices 100 and 200 described above. A main memory 1600 and an auxiliary storage 1700 may be provided separately from the CPU 1500. The main memory 1600 may include a dynamic random access memory (DRAM) device.

In some cases, the electronic device architectures may be implemented in the form in which unit computing devices and unit memory devices are adjacent to each other on one chip without any distinction between sub-units.

FIG. 13 is a block diagram of an electronic apparatus according to an embodiment.

The electronic apparatus 1900 may constitute a wireless communication device or a device capable of transmitting and/or receiving information in a wireless environment. The electronic apparatus 1900 may include a controller 1910, an input/output device (I/O) 1920, a memory 1930, and a wireless interface 1940, and these components may be interconnected to each other through a bus 1950.

The controller 1910 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The input/output device 1920 may include at least one of a keypad, a keyboard, and a display. The memory 1930 may be used to store instructions executed by controller 1910. For example, the memory 1930 may be used to store user data. The electronic apparatus 1900 may use the wireless interface 1940 to transmit/receive data through a wireless communication network. The wireless interface 1940 may include an antenna and/or a wireless transceiver. In some embodiments, the electronic system 4200 may be used in a communication interface protocol of a variety of communication systems, for example, code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), and/or wide band code division multiple access (WCDMA). The electronic apparatus 1900 may include the semiconductor devices 100 and 200 described above in the controller 1910, memory 1930, or other portions.

FIG. 14 of a display apparatus according to an embodiment.

Referring to FIG. 14, the display apparatus 1400 may include a display driver IC (DDI) 1420 including a controller 1402, a power supply circuit 1404, a driver block 1406, and a memory block 1408. The controller 1402 receives and decodes a command applied from a main processing unit (MPU) 1422, and controls each block of the DDI 1420 to implement an operation according to the command. The power supply circuit unit 1404 generates a driving voltage in response to the control of the control unit 1402. The driver block 1406 drives a display panel 1424 using the driving voltage generated by the power supply circuit unit 1404 in response to the control of the controller 1402. The display panel 1424 may be a liquid crystal display panel or a plasma display panel. The memory block 1408 is a block for temporarily storing commands input to the controller 1402 or control signals output from the controller 1402, or for storing necessary data, and may include a memory, such as RAM or ROM. The power supply circuit unit 1404 and the driver block 1406 may include the electronic device according to the embodiment described above. The display apparatus 1400 may include the semiconductor devices 100 and 200 described above in the controller 1402, memory block 1408, driver block 1406, MPU 1422, or other portions.

As described above, in the semiconductor devices 100 and 200 of the above example embodiments, the second two-dimensional material layers 131 and 132 or the second two-dimensional material layers 231 and 232 electrically connected to the at least one first two-dimensional material layer 120 or 220 forming a channel layer are in planar contact with the source and drain electrodes 141 and 142, thereby reducing the contact resistance therebetween. In addition, the second two-dimensional material layers 131 and 132 or the second two-dimensional material layers 231 and 232 are grown through edge epitaxy on end portions of the at least one first two-dimensional material layer 120 or 220, thereby reducing the contact resistance between the second two-dimensional material layers 131 and 132 or 231 and 232 and the at least one first two-dimensional material layer 120 or 220. While embodiments have been described, the embodiments are merely examples, and it will be understood by those of ordinary skill in the art that various modifications may be made in the embodiments.

One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

SEMICONDUCTOR DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF FABRICATING THE SAME

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