A semiconductor device and manufacture of that device is presented in which embodiments are directed to a semiconductor device and a method of manufacture therefore that uses a combination of a plasma etch and a soft etch to improve silicidation of gate electrodes.
Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today's ever shrinking and changing transistor devices. One of the principle reasons the industry is investigating replacing the polysilicon gate electrodes with metal gate electrodes is to solve problems of poly-depletion effects and boron penetration for future CMOS devices. Traditionally, a polysilicon gate electrode with an overlying silicide was used for the gate electrodes in CMOS devices. However, as device feature sizes continue to shrink, poly depletion and gate sheet resistance become serious issues when using polysilicon gate electrodes.
Accordingly, metal gates have been proposed. However, in order to optimize the threshold voltage (Vt) in high-performance devices, the metal gates need tunable work functions. For instance, the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1˜4.4 eV for NMOS and 4.8˜5.1 eV for PMOS.
Recently, silicided metal gates have been investigated based on the extension of existing self-aligned silicide (SALICIDE) technology. In this approach, polysilicon is deposited over the gate dielectric. A metal is deposited over the polysilicon and reacted to completely consume the polysilicon resulting in a fully silicided metal gate, rather than a deposited metal gate. The silicided metal gate provides a metal gate with the least perturbation to the conventional process and avoids contamination issues. Furthermore, poly doping has been shown to affect the work function of the silicided metal gates.
Complications can arise, however, during the silicidation process. For example, in some conventional processes and for reasons not fully known, all of the gate electrodes are not fully silicide as desired. In such instances, a number of electrodes may not get silicide, which causes yield loss and reliability issues.
Accordingly, what is needed in the art is a silicidation process that avoids the deficiencies of the conventional processes discussed above.
In one embodiment, the method comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, and a nitride-containing layer is placed over the oxide layer. A plasma etch is conducted to remove portions of the nitride-containing layer and the oxide layer that are located over the gate electrode and expose a surface of the gate electrode. In this embodiment, the plasma etch includes using a gas flow comprising CH2F2, CF4, O2, and an inert gas. The flow rate of CH2F2 is about 90 sccm, the flow rate of CF4 is about 30 sccm, the flow rate of O2 is about 15 sccm, and the flow rate of the inert gas is about 50 sccm. The plasma etch is conducted at a pressure of about 5 millitorr, at a power of about 550 watts, and at a bias of about 300 volts. Subsequent to the plasma etch, a soft etch is conducted on the surface of the gate electrode. In this particular embodiment, the soft etch includes using SF6, wherein a flow rate of SF6 is about 5 sccm and is conducted at a power of 200 watts with a bias of about 0.0 volts and at a pressure of about 3 millitorr. The gate electrode is silicided with a metal subsequent to conducting the soft etch.
In another embodiment, a method of manufacturing a semiconductor device comprises placing a first oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a nitride-containing layer over the oxide layer, placing a second oxide layer over the nitride-containing layer, and removing a portion of the second oxide layer to expose the nitride-containing layer. This embodiment further includes conducting a plasma etch to remove portions of the nitride-containing layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode. The plasma etch is selective to polysilicon and has an oxide/nitride selectivity ranging from about 0.4 to about 1.0, an oxide/polysilicon selectivity ranging from about 13.0 to about 40.0. A soft etch is conducted subsequent to the plasma etch and includes using an inorganic-based fluorine containing gas and an inert gas, wherein the soft etch has a nitride/oxide selectivity ranging from about 1.0 to about 1.2 and an oxide/polysilicon selectivity of about 0.7. The gate electrode is silicided with a metal subsequent to conducting the soft etch.
Another embodiment provides a method of manufacturing a semiconductor device, comprising placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch.
Another embodiment provides a semiconductor device that comprises a plurality of silicided gate electrodes having source/drains that are located in wells associated therewith. The silicided gate electrodes are formed by: conducting a plasma etch to remove portions of the nitride-containing layer and the oxide layer located over the gate electrode and expose a surface of the gate electrode. The plasma etch includes using a gas flow comprising CH2F2, CF4, O2, and an inert gas. A flow rate of CH2F2 is about 90 sccm, a flow rate of CF4 is about 30 sccm, a flow rate Of O2 is about 15 sccm, and a flow rate of the inert gas is about 50 sccm. The plasma etch is conducted at a pressure of about 5 millitorr, at a power of about 550 watts and at a bias of about 300 volts; conducting. A soft etch is conducted on the surface of the gate electrode and includes using an inorganic-based fluorine containing gas and an inert gas subsequent to conducting the plasma etch. A flow rate of SF6 is about 5 sccm and the soft etch is conducted at a power of about 200 watts with a bias of about 0.0 volts and at a pressure of about 3 millitorr. The gate electrode is silicided with a metal subsequent to conducting the soft etch. The semiconductor device further includes dielectric layers located over the silicided gate electrodes and interconnects formed over or within the dielectric layers that interconnect the silicided gate electrodes and the source/drains.
For a better understanding, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the illustrated embodiment of
The silicided gate electrodes 150 may also include a dopant or combination of several types of dopants therein. The dopant, such as boron, phosphorous, arsenic or another similar dopant based on whether the semiconductor device 100 is operating as a PMOS device or an NMOS device, is configured to tune the minimum energy required to bring an electron from the Fermi level to the vacuum level, or the so called work function.
The gate structure 130 may further include conventional gate sidewall spacers 160 flanking both sides of the silicided gate electrode 150 and gate oxide 140. The gate sidewall spacers 160 may each include one or more different layers. For instance the gate sidewall spacers 160 may also include nitride-containing spacers 163 and sidewall oxides 165 and 168. It should be noted that the gate sidewall spacers 160 may comprise many different types and numbers of layers.
The semiconductor device 100 may also include conventional source/drain regions 170 located within the substrate 110 and proximate the gate oxide 140 and within a moat region 170a located between the gate electrodes 150. Located within the source/drain regions 170 are silicided source/drain contact pads 180, on which contact structures 185 are located. The silicided source/drain contact pads 180 in one embodiment may comprise nickel silicided source/drain contact pads. Nonetheless, other silicidation materials could be used to form the silicided source/drain contact pads 180 and remain within the scope of the present invention. The silicided source/drain contact pads 180 may have a depth into the source/drain regions 170 ranging from about 10 nm to about 30 nm, among others.
In one embodiment, the etch 710 is conducted to remove the protective layer 410 and the underlying oxide layer 310 that are located over the gate electrodes 320, yet is selective to the material that comprises the gate electrodes 320. The etch 710 is configured to uniformly remove the protective layer 410 and the oxide layer 310 and have a controlled landing on the gate electrode 320. In one aspect, the gate electrodes 320 may be polysilicon. In such instances, the etch 710 would be selective to polysilicon; that is, the etch 710 etches the polysilicon at a significantly slower rate (as much as about 13 times slower) than the protective layer 410 or the oxide layer 310. This selectivity is beneficial in providing a controlled landing on the gate electrodes 320 so that the gate electrodes 320 are not significantly damaged or over-etched. This selectivity is also beneficial to prevent over-etch of the gate electrodes 320 in those areas where the CMP might have removed more of the protective layer 410 and the oxide layer 310. Moreover, etch 710 is configured to uniformly etch the oxide and nitride.
For example, in those embodiments where the gate electrodes 320 comprise polysilicon, the etch 710 may have an oxide/polysilicon selectivity ranging from about 13 to about 40.0. In another embodiment, the protective layer 410 contains nitrogen, and in this particular embodiment, the oxide/nitride selectivity may range from about 0.4 to about 1.0, and the oxide/polysilicon selectivity may also range from about 13 to about 40 as with the previous embodiment. As seen, the etch rate of the oxide/nitride is similar, but is much higher than the etch rate of the polysilicon. This facilitates a uniform removal of the protective layer 410 and the oxide layer 310 and provides a controlled landing on the gate electrodes 320.
In another aspect where the protective layer 410 includes nitrogen, the oxide/nitride selectivity may be about 0.9, the nitride/polysilicon selectivity may be about 14.4 and the oxide/polysilicon selectivity may be about 13.1.
An example of the type of chemistry that can be used in etch 710 is a gas flow comprising CH2F2, CF4, O2, and an inert gas, such as He or Ar. In one embodiment, the flow rate of CH2F2 may be about 90 sccm, the flow rate of CF4 may ranging from about 30 sccm to about 45 sccm, the flow rate of O2 may range from about 10 to about 15 sccm, and the flow rate of the inert gas may be about 50 sccm. Further, the etch 710 may be conducted at a pressure of about 5 to 8 millitorr, at a power of about 500 watts, and at a voltage bias of about 300 volts. In one case, a flow rate of CF4 of about 30 sccm and a flow rate of O2 of about 15 yielded good results. Additionally, the polysilicon etch rate may range from about 6.7 nm/min to about 9.8 nm/min and the oxide etch rate may range from about 95.3 nm/min to about 87.9 nm/min, with 6.7 nm/min and 87.9 min, in one embodiment, obtaining good results.
The etch is conducted until the protective layer 410 and the oxide layer 310 are removed from over the top portion of the gate electrodes 320 as shown in
In view of the discovery of the existence of film 720, a soft etch 725 is conducted to remove the film 720. As used herein, a soft etch is an etch that uses an inorganic-based fluorine chemistry (i.e., one that does not contain carbon) and uses a low bias potential energy level (e.g., one that is very close to zero volts) during the etch. Due to the very low potential energy levels, the soft etch effectively does not contain an ion etching. As such, the film 720 can be removed without over etching the gate electrodes 320. An inert gas, such as helium or argon, may also be used in the soft etch 725. In one embodiment, the soft etch 725 has a nitride/oxide selectivity ranging from about 1.0 to about 1.2 and an oxide/polysilicon selectivity of about 0.7.
In another embodiment, the inorganic fluorine gas may be F2 or NF3, and in yet another embodiment that yields good results, the inorganic-based fluorine gas is SF6. In one aspect of this embodiment, the flow rate of SF6 is about 5 sccm and the soft etch is conducted at a power of about 200 watts with a bias of about 0.0 volts and at a pressure of about 3 millitorr The soft etch is conducted for until the film 720 is removed, as shown in
Following the removal of the film 720, a metal layer 810 is deposited over the gate electrodes 320, as shown in
The metal layer 810 may be nickel or cobalt or a combination thereof. In those embodiments where the metal layer 810 is nickel, an exemplary silicide process comprises placing a blanket of nickel layer over the gate electrodes 320. As it takes approximately 1 nm of nickel to fully silicidize approximately 1.8 nm of polysilicon, the thickness of the blanket layer of nickel should be at least 56% of the thickness of the gate electrode 320. To be comfortable, however, it is suggested that the thickness of the layer of nickel should be at least 60% of the thickness of the gate electrode 320. Thus, where the thickness of the gate electrode 320 ranges from about 50 nm to about 150 nm, as described above, the thickness of the blanket layer of nickel should range from approximately 30 nm to about 90 nm. It should also be noted that the blanket layer of metal layer 810 may comprise a number of different metals or combinations of metals, such as nickel and cobalt, while staying within the scope of the present invention. The nickel layer and the gate electrodes 320 are subjected to a thermal anneal having a temperature ranging from about 400 degrees centigrade to about 600 degrees centigrade and for a period of time ranging from about 10 seconds to about 100 seconds. It should be noted, however, that the silicidation process may vary depending on the amount of silicidation that is desired and the materials that are used to silicide the gate electrodes 320. For example, if the gate electrodes 320 are silicided with a combination of cobalt and nickel, then the silicidation process parameters and percentages of materials used will be different than those just stated above. Those who are skilled in the art will understand how to achieve the desired degree of silicidation when using such metal combinations.
After siliciding the gate electrode 320, any remaining or unreacted metal materials can be removed using conventional processes. It should be noted that the silicide does not form on the moat region 216 or the source/drains 228 at this time because the protective layer 410 and the oxide layer 310 block the silicidation process from affecting those regions.
Following the silicidation process and removal of the excess metal layer 810, the remaining portions of the protective layer 410 and the oxide layer 310. A conventional source/drain silicidation process may then be conducted to form silicidation contacts 910 and arrive at the semiconductor device 200 shown in
Those skilled in the art will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.