Patent Application
20100156500
This application is based upon and claims the benefit of the priority of Japanese patent application No. 2008-327620, filed on Dec. 24, 2008, the disclosure of which is incorporated herein in its entirety by reference thereto.
This invention relates to a semiconductor device, an output circuit and to a method for controlling an input/output buffer circuit in the semiconductor device. More particularly, this invention relates to a semiconductor device having an output circuit thought to be used at respective different power supply voltages, and to the output circuit. It also relates to a method for controlling an input/output buffer circuit in a semiconductor device thought to be used at respective different power supply voltages.
A semiconductor device having a conventional semiconductor device including an output buffer circuit is shown in Patent Document 1. This semiconductor device includes a plurality of output buffer circuits connected in parallel one with another, The driving capability of an output driver may be varied by a user in keeping with the peripheral circuit connected to outside.
JP Patent Kokai Publication No. JP-H05-55891A
The entire disclosures of above Patent Document is incorporated herein by reference thereto. The following analyses are given according to the views of the present invention.
The following analysis is made from the side of the present invention. Among up-to-date semiconductor products, there are those that are of approximately equal functions and differ only with respect to power supply voltages that are in use. In recent DRAMs, the tendency is towards using a lower power supply voltage. In these DRAMs, power supplies are conventionally developed as separate products. The reason is that, if the power supply voltages differ, it becomes necessary to perform designing with the use of the different driving capabilities of an output buffer circuit or with the use of the different input threshold levels of the input buffer circuit. It is thus necessary to develop a power supply from one power supply voltage to another, with the result that costs for development or for inventory management for mass-produced devices are increased.
In a first aspect, the present invention provides a semiconductor device comprising a signal terminal, a power supply terminal supplied with a power supply voltage, an output circuit including first and second output buffer circuits, and a power supply voltage discrimination circuit. Each of the first and second output buffer circuits is supplied with the power supply voltage from the power supply terminal. The output circuit receives inner output signals to drive the signal terminal. A power supply voltage discrimination circuit performs discrimination of a potential level of the power supply voltage to control an operation of the output circuit based on a result of the discrimination. The first output buffer circuit is activated and the second output buffer circuit is deactivated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a first potential. Both of the first and second output buffer circuits are activated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a second potential.
In a second aspect, the present invention provides a semiconductor device comprising a plurality of input/output terminals, a plurality of input terminals, a power supply terminal, a plurality of output circuits, a plurality of first input circuits, a plurality of second input circuits and a power supply discrimination circuit. The output circuits are each provided in association with the input/output terminals. Each of the output circuits includes first and second output buffer circuits that are supplied with a power supply voltage from the power supply terminal and that receive inner output signals to drive the input/output terminal associated therewith. Each of the first input circuits is associated with one of the input/output terminals and includes first and second input buffer circuits connected to the associated one of the input/output terminals. The second input circuits are each associated with one of the input terminals. Each of the second input circuits includes third and fourth input buffer circuits connected to an associated one of the input terminals. The power supply discrimination circuit discriminates the power supply voltage to control the operation of the output circuit based on the result of decision of the power supply voltage. If the power supply voltage discrimination circuit has decided that the power supply voltage is at the first potential, the first output buffers and the first and third input buffer circuits are activated, while the second output buffer circuit and the second and fourth input buffer circuits are deactivated. If the power supply voltage discrimination circuit has decided that the power supply voltage is at the second potential, the first and second output buffer circuits and the second and fourth input buffer circuits are activated and the first and third input buffer circuits are deactivated.
In a third aspect, the present invention provides an output circuit comprising first and second output buffer circuits, and a power supply voltage discrimination circuit. The first and second output buffer circuits receive inner output signals and are thereby run in operation. Output nodes of the first and second output buffer circuits are connected in common. The power supply voltage discrimination circuit discriminates a power supply voltage to control the operation of the first and second output buffer circuits based on the result of discrimination. The first output buffer circuit is activated and the second output buffer circuit is deactivated in case the power supply discrimination circuit has decided that the power supply voltage is at the first potential. Both of the first and second output buffer circuits are activated in case the power supply discrimination circuit has decided that the power supply voltage is at the second potential.
In a forth aspect, the present invention provides a semiconductor device comprising a signal terminal, a power supply terminal supplied with a power supply voltage, first and second output buffer circuits each supplied with the power supply voltage from the power supply terminal, and a power supply voltage discrimination circuit activating selected one or ones of the first and second output buffer circuits in response to a electrical potential of the power supply voltage.
The meritorious effects of the present invention are summarized as follows.
According to the present invention, such a semiconductor device whose driving capabilities for e.g. an output buffer differ with different power supply voltages used may be obtained with ease as the circuit is scarcely increased in circuit area.
The above features and advantages of the present invention will be more apparent from the following description of certain preferred exemplary embodiments taken in conjunction with the accompanying drawings.
Preferred exemplary embodiments of the present invention will now be described by referring to the drawings as necessary. It should be noted that particular drawings and reference numerals used therein, if referred to in the following description, are so referred to only by way of illustration, and are not intended to limit other possible variations of the exemplary embodiment of the present invention.
The semiconductor device according to exemplary embodiments of the present invention includes a signal terminal S1 having at least the function of an output terminal, a power supply terminal VDD, an output circuit 1, and a power supply voltage discrimination circuit (2, 22), as shown in
The semiconductor device of the exemplary embodiments also includes a level shift circuit (5, 6) for converting the voltage level of the inner output signals (TI, BI) into that of the power supply voltage level VDD, as shown for example in
With the semiconductor device according to the exemplary embodiments, the first and second output buffer circuits each include a plurality of P-channel output buffers (P1 to P6) and a plurality of N-channel output buffers (N1 to N6), as shown in
With the semiconductor device according to the exemplary embodiments, the number of the P-channel output buffers (P1 to P6) of the first and second output buffer circuits (3, 4) turned on simultaneously or the number of the N-channel output buffers (N1 to N6) of the first and second output buffer circuits turned on simultaneously is controlled by a set of driver intensity signal (DF, DH and DQ of
The power supply voltage discrimination circuit (2, 22) of the semiconductor device according to the exemplary embodiments includes voltage comparison circuits (C1, C2) as shown for example in
The power supply voltage discrimination circuit (2, 22) of the semiconductor device according to the exemplary embodiments discriminates the power supply voltage by data stored in the non-volatile storage circuit 12, as shown for example in
With a semiconductor device according to the exemplary embodiments, the signal terminal is an input/output terminal (S1, S3), as shown in
The semiconductor device according to the exemplary embodiments further comprises input terminals (S2, S4) and third and fourth input buffer circuits (33, 34, 38, 39) connected to the input terminals (S2, S4), as shown in
The semiconductor device according to the exemplary embodiments includes a plurality of input/output terminals (S1, S3), a plurality of input terminals (S2, S4), a power supply terminal VDD, and a plurality of output circuits (1, 35), as shown for example in
An output circuit according to the exemplary embodiments includes first and second output buffer circuits (3, 4) that receive inner output signals and that are thereby run in operation, and a power supply voltage discrimination circuit (2, 22), as shown in
The method according to the exemplary embodiments controls input/output buffer circuits (1, 31, 32, 35, 36, 37) in a semiconductor device 100 to which a plurality of different power supply voltages may possibly be supplied. The semiconductor device 100 includes first and second output buffer circuits (3, 4) and first and second input buffer circuits (31, 32, 36, 37). The first and second output buffer circuits receive common inner output signals (S1T, S1B, S3T, S3B) and are thereby run in operation. Outputs of the first and second output buffer circuits are connected to common input/output terminals (S1, S3). Input nodes of the first and second input buffer circuits (31, 32, 36, 37) are connected to the input/output terminals (S1, S3). The method comprises activating the first output buffer circuit 3 and the first input buffer circuits (31, 36) and deactivating the second output buffer circuit 4 and the second input buffer circuits (32, 37) when a first power supply voltage (1.8V) is supplied as the power supply voltage. The method also comprises activating the first and second output buffer circuits (3, 4) and the second input buffer circuits (32, 37) and deactivating the first input buffer circuits (31, 36) when a second power supply voltage (1.2V) is supplied as the power supply voltage. Thus, the first output buffer circuit is activated, as is the second output buffer circuit, when the power supply voltage is at the second potential level. Hence, an optimum driving capability may be obtained without substantially increasing the area of the output buffer circuit, irrespectively of whether the power supply voltage is at the first potential or at the second potential. In addition, since the switching between taking data from the first input buffer circuit and taking data from the second input buffer circuit is made in dependence upon the power supply voltage, the input threshold level of the input buffer circuit may be optimized from one power supply voltage to another. The present invention is now described in detail with reference to Examples.
The power supply terminal VDD delivers power to an output circuit 1. The voltages needed by internal circuits, other than the output circuit 1, are generated as necessary by a voltage decreasing circuit or a voltage increasing circuit, from the power supply VDD, and delivered to respective parts within the semiconductor device.
The signal terminal S1 is a signal terminal at least having the function of an output terminal. The signal terminal S1 may also be an input/output terminal, in a manner not shown in
Data T and B signals, generated by an internal circuit of the semiconductor device 100, are latched in data latches 7 and 8 of the output circuit 1 in synchronism with a clock signal CLK. The signal terminal S1 is driven on the basis of the so latched data signals.
The data T and B signals are complementary 1-bit signals used for controlling a P-channel output buffer and an N-channel output buffer of an output circuit, respectively. The data T signal and the data B signal are delivered to data latches 7 and 8, respectively, and thence supplied to level shift circuits 5 and 6, after having the timings adjusted as output signals. The level shift circuits 5 and 6 are used for converting the signal voltage level. That is, these level shift circuits convert the low voltage signal of the levels of a power supply VPERI of the internal circuit to the high voltage signal of the VDD level as the power supply of the output circuit. As the level shift circuit, a well-known level shift circuit, shown in
Output signals of the level shift circuits 5, 6 are respectively supplied to an output buffer circuit 3 for 1.8V, as a first output buffer circuit, and to an output buffer circuit 4 for 1.2V, as a second output buffer circuit. An E18 signal and an E12 signal, as control signals from a power supply discrimination circuit 2, are respectively supplied to the output buffer circuit 3 for 1.8V and to the output buffer circuit 4 for 1.2V. The power supply discrimination circuit 2 discriminates if the power supply voltage delivered from the power supply terminal VDD is 1.2V or 1.8V, and respectively outputs the signals E18 and E12 to the output buffer circuit 3 for 1.8V and to the output buffer circuit 4 for 1.2V. The signal E12 acts as enabling signal when VDD is 1.2V, while the signal E18 acts as enabling signal when VDD is 1.8V. These two enabling signals decide on the output buffer circuit, out of the output buffer circuit 3 for 1.8V and the output buffer circuit 4 for 1.2V, which is to be activated. Specifically, the output buffer circuit 3 for 1.8V is activated when one of the E18 signal and the E12 signal are HIGH in level, while being deactivated when both of the E18 signal and the E12 signal are LOW in level.
When the E12 signal is HIGH or LOW in level, the output buffer circuit 4 for 1.2V is activated or deactivated, respectively. As a consequence, the E12 signal goes HIGH in level, when VDD is 1.2V, so that both the output buffer circuit 3 for 1.8V and the output buffer circuit 4 for 1.2V are activated and are run in operation. It is thus possible to suppress the circuit area from increasing as compared to the case of simply operating only the output buffer circuit 4 for 1.2V in case the VDD is 1.2V.
A driving intensity controlling circuit 9 is a circuit that causes the driving capability of an output circuit to be changed depending on e.g. the load on the peripheral circuit. Driving intensity control signals DF, DH and DQ are coupled from the driving intensity controlling circuit 9 to each of the output buffer circuit 3 for 1.8V the output buffer circuit 4 for 1.2V. The DF signal is a full driving intensity signal, the DH signal is a half driving intensity signal and the DQ signal is a quarter driving intensity signal. It should be noted that, in case the driving intensity control signals DF, DH and DQ are all HIGH, both the output buffer circuit 3 for 1.8V and the output buffer circuit 4 for 1.2V are in full play. In case the DF signal is LOW in level and both the DH and DQ signals are HIGH in level, the output load driving capability of each of the output buffer circuit 3 for 1.8V and the output buffer circuit 4 for 1.2V is half of that of the circuits 3 and 4 when the latter are in full play. In case the DF and DH signals are LOW in level and only the DQ signal is HIGH in level, the output load driving capability of each of the output buffer circuit 3 for 1.8V and the output buffer circuit 4 for 1.2V is one quarter of that of the circuits 3 and 4 when the latter are in full play.
In the following description, it is presupposed that one of the E18 signal and the E12 signal is HIGH, with the output of the NOR gate R1 being LOW. At this time, the P-channel output buffer transistor P1 is turned on when a P-channel output buffer control signal TO is HIGH and the full driver intensity signal DF is HIGH. The N-channel output buffer transistor N1 is turned on when an N-channel output buffer control signal BO is LOW and the full driver intensity signal DF is HIGH. The logic states of the remaining output buffer transistors P2, N2, P3 and N3 are set so that the respective output buffer transistors will be turned on or off depending on the combination of the logic levels of the P-channel output buffer control signal TO and the N-channel output buffer control signal BO and the driver intensity control signals DH and DQ.
The transistor sizes of the P-channel output buffer transistor P1, N-channel output buffer transistor N1, the remaining P-channel output buffer transistors P2, P3 and the remaining N-channel output buffer transistors N2, N3 are set so that the driving capabilities of the transistors P1 and N1 will be twice those of the transistors P2, P3 and twice those of the transistors N2, N3. Specifically, the P-channel output buffer transistor P1 and the N-channel output buffer transistor N1 are of a gate width W equal to α, whereas the P-channel output buffer transistors P2, P3 and the N-channel output buffer transistors N2, N3 are each of a gate width E equal to α/2. Thus, out of the parallel connected P-channel output buffer transistors and the parallel connected N-channel transistors, those transistors which are turned on simultaneously may be controlled by the intensity control signals DF, DH and DQ to set the driving capabilities of the output buffer transistors to ½ or ¼ with ease.
An example configuration of the power supply discrimination circuit 2 of
In the above mentioned first and second example configurations of the power supply discrimination circuit, the power supply voltage delivered from outside to the power supply terminal VDD may be discerned without providing a new external terminal. The power supply voltage delivered from outside may possibly be set by such external terminal. This is however not desirable with a device, such as DRAM, regulated by reference prescriptions, because there lacks the provision of such new external terminals in the prescriptions. With the power supply voltage discrimination circuit according to the above mentioned first or second example configurations, the power supply voltage may be discerned without alteration of the prescriptions for the devices.
The way of deciding the transistor size of the output buffer transistors in
1.8/1.2=(α+β)/α (1)
For example, if α=300 [μm], β=150 [μm]. That is, if the power supply voltage VDD is 1.2V, not only the transistor of the output buffer circuit for 1.2V but the transistor of the output buffer circuit for 1.8V is activated simultaneously. Hence, the transistor size of the output buffer circuit for 1.2V may be reduced.
It is supposed that, with the power supply voltage VDD=1.2V, the transistor of the output buffer circuit for 1.8V is not activated simultaneously and only the transistor of the output buffer circuit for 1.2V is activated. It is then necessary that the transistor size of the second output buffer circuit for 1.2V is equal to 450 [μm] which is (α+β). That is, by simultaneously activating the output buffer circuit for 1.8V and the second output buffer circuit for 1.2V, in accordance with the present Example, it is possible to reduce the transistor size of the output buffer circuit for 1.2V by a factor of 3.
On a side downstream of the level shift circuits 5, 6, signals of voltage amplitudes differing in dependence upon the power supply voltage of VDD are applied to the respective transistors. As a first case, it is supposed that VDD=1.8V is supplied. In this case, the power supply voltage of 1.8V is applied to the gate of each transistor of the output buffer circuit 3 for 1.8V and to the gate of each transistor of the output buffer circuit 4 for 1.2V. It is thus desirable that each transistor of the output buffer circuit for 1.2V is constructed as a high voltage withstand transistor with a gate withstand voltage of not less than 1.8V. To prevent the sorts of the transistors from increasing wastefully, it is desirable to use the transistor of the same withstand voltage for the transistor of the output buffer circuit 3 for 1.8V and for the transistor of the second output buffer circuit 4 for 1.2V.
As a second case, it is supposed that VDD=1.2V is supplied. In order for both of the output circuits to be in operation, the transistors (NMOS transistors) of the output buffer circuit 3 for 1.8V need to be run in operation with the gate voltage of 1.2V. That is, the threshold value voltage of each NMOS transistor of the output buffer circuit 3 for 1.8V needs to be not higher than 1.2V.
The above mentioned Example 1 is directed to a system that uses two power supplies. The present invention may also be directed to a system that uses three or more power supplies. If the present invention is applied to such system, employing three or more power supplies, the withstand voltage of each transistor may be made to match to the highest power supply. On the other hand, the threshold voltage of each transistor, in particular an NMOS transistor, may be made to match to the lowest power supply.
To the input/output terminal S1, there are connected, in addition to the output circuit 1 of Example 1, an S1 input buffer circuit 18, as a 1.8V system input circuit, and an S1 input buffer circuit 12, as a 1.2V system input circuit. The terminal S1 thus has, in addition to the function of an output terminal of Example 1, the function as an input terminal that takes a signal, output from the controller 40, into the inside of the semiconductor device 200. The input circuit separately has an input circuit for the 1.8V system and another input circuit for the 1.2V system, so that the input threshold levels for the case of inputting the 1.8 V system signal and for the case of inputting the 1.2 V system signal may be set independently. As voltages that become the reference of the input threshold levels, a reference voltage signal VREF1 is input to the input circuit of the 1.8V system, and another reference voltage signal VREF2 is input to the input circuit of the 1.2V system. An S1 output circuit 1 is the same in circuit configuration to the circuit 1 of Example 1 and hence the description thereof is dispensed with.
An S3 output circuit 35, connected to the input/output terminal S3, an S3 input buffer circuit 18, as an input circuit for the 1.8V system, and an S3 input buffer circuit 12, as an input circuit for the 1.2V system, are the same in circuit configuration to the output circuits and the input buffer circuits connected to the input/output terminal S1.
To the input terminal S2 or to the input terminal S4, no output circuit is connected, but an input circuit for the 1.8V system and an input circuit for the 1.2V system are connected. The functions of the input terminals S2, S4 correspond to the functions of the input/output terminals S1, S3 less the functions as the output terminals. That is, the input terminals S2, S4 possess the functions only of taking signals output from the controller 40 into the inside of the semiconductor device 200.
The power from the power supply VDD is directly supplied to the output circuits 1, 35, however, the power from an internal power supply VPERI is supplied to the input buffer circuits (31 to 34 and 36 to 39), in a manner not shown in
The semiconductor device 200 includes a power supply voltage discrimination circuit 22 that controls the respective output circuits, input buffer circuits of the 1.8V system and input buffer circuits of the 1.2V system. In contradistinction from the power supply discrimination circuit 2 that outputs only the E18 signal and the E12 signal of Example 1, the power supply voltage discrimination circuit 22 outputs a B18 signal and a B12 signal, in addition to the E18 signal and the E12 signal. The B18 signal controls the input buffer circuits (31, 33, 36, 38) of the 1.8V system, and affords a constant current bias voltage to the associated input buffer circuits when the power supply voltage is 1.8V. The B18 signal becomes OV when the power supply voltage is different from 1.8V. In similar manner, the B12 signal controls the input buffer circuits (32, 34, 37, 39) of the 1.2V system, and affords a constant current bias voltage to the input buffer circuits when the power supply voltage is 1.2V. The B12 signal becomes OV when the power supply voltage is different from 1.2V. It should be noted that the signals B18 and B12 may readily be generated by a well-known constant current source circuit and a current mirror circuit, based on the E18 and E12 signals, respectively. Hence, detailed description of the internal circuit is dispensed with.
When the power supply voltage is 1.8V, the input buffer circuits 31, 33, 36 and 38 of the 1.8V system and the output buffer circuits for 1.8V of the output circuits 1, 35 are activated by the E18, E12, B18 and B12 signals output from the power supply discrimination circuit 22. On the other hand, the input buffer circuits 32, 34, 37 and 39 of the 1.2V system and the output buffer circuits for 1.2V of the output circuits 1, 35 are deactivated. Also, when the power supply voltage is 1.2V, the input buffer circuits 32, 34, 37 and 39 of the 1.2V system, the output buffer circuits for 1.2V and the output buffer circuits for 1.8V and for 1.2V of the output circuits 1, 35 are activated, while the input buffer circuits 31, 33, 36 and 38 of the 1.8V system are deactivated.
The drains of the P-channel transistor P51 and the N-channel transistor N51 are connected together and output as an inner input signal. Referring to
By using, as an input buffer circuit, a voltage comparator circuit with a different reference voltage in dependence upon the voltage delivered from the power supply terminal VDD, it is possible to implement an input buffer circuit having an optimum input level with respect to plural sorts of power supply voltages.
The above Examples are directed to a case where power supply voltage terminals are used with two sorts of power supply voltages of 1.8V and 1.2V. However, the number of the power supplies or the values of the power supply voltages are naturally not limited to those of the Examples, such that three or more power supplies may also be used.
Other preferable modes of the present invention are summarized in the following.
A method for controlling an input/output buffer circuit in a semiconductor device to which a plurality of different power supply voltages may possibly be supplied;
said semiconductor device including:
first and second output buffer circuits that receive a common inner output signal and that are thereby run in operation; said first and second output buffer circuits having output nodes connected to a common input/output terminal; and
first and second input buffer circuits having input nodes connected to said input/output terminal;
said method comprising:
activating said first output buffer circuit and said first input buffer circuit and deactivating said second output buffer circuit and said second input buffer circuit when a first power supply voltage is supplied as said power supply voltage; and
activating said first and second output buffer circuits and said second input buffer circuit and deactivating said first input buffer circuit when a second power supply voltage is supplied as said power supply voltage.
It should be noted that other objects, features and aspects of the present invention will become apparent in the entire disclosure and that modifications may be done without departing the gist and scope of the present invention as disclosed herein and claimed as appended herewith.
Also it should be noted that any combination of the disclosed and/or claimed elements, matters and/or items may fall under the modifications aforementioned.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-327620 | Dec 2008 | JP | national |
