Patent Application
20110272783
The present invention generally relates to a semiconductor device with a bipolar transistor and a capacitor and, more particularly, to a semiconductor device that has a downsized circuit area.
The bipolar transistor has advantages such as high transconductance, low 1/f noise, constant Vbe voltage drop, high withstanding volate and current, high-speed switching, high gain and high current drivibility. Accordingly, the bipolar transistor has attracted tremendous attention in applications such as linear IC's, mixed-signal IC's and analog IC's.
However, the bipolar transistor based IC's are less integrated because the bipolar transistor occupies a larger area on the chip. The conventional IC with a bipolar transistor and a capacitor is as shown in
Since the current of the bipolar transistor flows in the n-type epitaxial layer 14 and the first electrode 181 of the capacitor is embedded in the n-type epitaxial layer 14, the p-type buried layer 145 and the insulator 147 are required to isolate the devices to prevent interference. It results in large circuit area.
Moreover, since the protective insulator 149 is formed by oxidation in a furnace after a shallow n+-doped layer (as the first electrode 181) is formed on the n-type epitaxial layer 14, the capacitance of the capacitor is low because the oxide layer has to be thick enough for the heavily doped n+ ions.
It is one object of the present invention to provide a semiconductor device with a bipolar transistor and a capacitor that has a downsized circuit area.
It is another object of the present invention to provide a semiconductor device with a bipolar transistor and a capacitor, wherein the capacitor is formed on an isolating insulator that isolates the transistors.
It is still another object of the present invention to provide a semiconductor device with a bipolar transistor and a capacitor, wherein the capacitor is a PIP capacitor, a PIM capacitor or a MIM capacitor.
It is still another object of the present invention to provide a semiconductor device with a bipolar transistor and a capacitor, wherein the conventional isolating insulator that isolates the transistors and the capacitors are not required, leading to a reduced circuit area.
The present invention provides a semiconductor device with a bipolar transistor and a capacitor, the semiconductor device comprising: a substrate; an epitaxial layer formed on the substrate; a plurality of isolating buried layers dividing the epitaxial layer into a plurality of device regions; a plurality of isolating insulators formed on the isolating buried layers, respectively; a plurality of bipolar transistors formed in the device regions, respectively; a protective insulator covering the device regions and the isolating insulators; and at least one capacitor formed on the protective insulator and corresponding to the isolating insulator.
The present invention further provides a semiconductor device with a bipolar transistor and a capacitor, the semiconductor device comprising: a substrate; an epitaxial layer formed on the substrate; a plurality of isolating buried layers dividing the epitaxial layer into a plurality of device regions; a plurality of isolating insulators formed on the isolating buried layers, respectively; a plurality of bipolar transistors formed in the device regions, respectively; a protective insulator covering the device regions and the isolating insulators; and at least one capacitor formed on the protective insulator and corresponding to an area excluding the bipolar transistor.
The objects and spirits of the embodiments of the present invention will be readily understood by the accompanying drawings and detailed descriptions, wherein:
The present invention can be exemplified but not limited by various embodiments as described hereinafter.
Please refer to
There are a variety of transistors such as the first bipolar transistor 26 and the second bipolar transistor 28 formed in the device regions. A capacitor 29 may be formed on the isolating insulator 247.
Taking npn transistors for example, the substrate 22 is a p-type substrate, the epitaxial layer 24 is an n-type epitaxial layer, and the isolating buried layer 245 is a p-type buried layer. In each device region, an n+-type buried layer 241 is formed between the substrate 22 and the epitaxial layer 24. Furthermore, two n+-doped regions as the emitter region 265, 285 and the collector region 261, 281 and a p+-doped region as the base region 263, 283 are formed in the top portion of the epitaxial layer 24 of each device region 26, 28.
After a protective insulator 249 is deposited on each of the devices, a plurality of via holes are formed corresponding to the collector region 261, 281, the base region 263, 283 and the emitter region 265, 285. The via holes are then filled with polysilicon to form collector contacts 262, 282, base contacts 264, 284 and emitter contacts 266, 286.
During the formation of the contacts, a first electrode 291 is formed on the protective insulator 249 corresponding to the isolating insulator 247. Then, an insulator 293 and a second electrode 295 are deposited on the first electrode 291 in order. Consequently, a semiconductor device 20 with a bipolar transistor and a capacitor is completed.
Please refer to
Moreover, the manufacturing steps of the capacitor 39 can be combined with the manufacturing steps of the bipolar transistors 36, 38. For example, the first electrode 291 of the capacitor 39 is formed during the formation of the contacts of the bipolar transistors and deposited on the protective insulator 249 corresponding to the isolating insulator 247. The insulator 293 of the capacitor 39 is formed during the formation of the insulator 33 that covers the contacts. Moreover, the second electrode 295 of the capacitor 39 is a part of the patterned metal layer 35 of the semiconductor device 30 and thus is formed with the collector electrodes 361, 381, the base electrodes 363, 383, the emitter electrodes 365, 385 and the first electrode contact 391 at the same time.
Please refer to
In the semiconductor device of the present invention, the capacitor can be a polysilicon-insulator-polysilicon (PIP) capacitor, a polysilicon-insulator-metal (PIM) capacitor or a metal-insulator-metal (MIM) capacitor. The insulator of the capacitor can be an oxide layer (preferably, an silicon dioxide layer) to achieve low cost. Alternatively, the insulator of the capacitor can also be implemented using an oxide-nitride-oxide (ONO) layer to form a sandwiched structure for higher capacitance.
Accordingly, the present invention discloses a semiconductor device with reduced circuit area, less manufacturing steps and lowered manufacturing cost.
Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to persons skilled in the art. This invention is, therefore, to be limited only as indicated by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 099208509 | May 2010 | TW | national |
