Patent Application
20050280053
The present invention is generally directed to a semiconductor device and, more specifically, to a semiconductor device with a diagonal gate signal distribution runner.
Conventional metal-oxide semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT) power devices have usually been designed with a cellular structure, which includes thousands of elementary cells integrated within a semiconductor die. Each cell has included a transistor which is connected in parallel to the transistors of the other cells to contribute to an overall current associated with the power device. In general, each cell includes a gate region, which is covered by a thin electrically insulative layer, e.g., a gate oxide layer. The gates of the cells are interconnected with a conductor, e.g., a polysilicon or metal layer, that is formed on a top surface of the device. The remaining top surface of the semiconductor device is typically covered by another conductor, which contacts and interconnects the source region of all of the cells. In general, the cellular structure allows for the achievement of relatively low voltage drop across the power device, i.e., low drain-to-source resistance, when it is in the on-state and, thus, relatively low power dissipation for the power device.
With reference to
In general, designers have attempted to design gate signal ring and fingers to allow parallel cells within a semiconductor device to turn on and off with minimal propagation delay between the cells and to allow current to flow in a uniform manner across the power device. The gate signal runners have been made of a variety of materials, e.g., metals, polysilicon or a combination of metal and polysilicon, and have had various configurations depending on the physical dimensions and operating frequency of the device. For devices operating at lower frequencies, a relatively simple gate structure that traverses the periphery of the device has generally been suitable. However, devices operating at higher frequencies have generally required additional gate fingers (see
Gate pads have usually been centered along one of the edges of the semiconductor device or located at a center of the device. In a typical semiconductor device that implements wire bonding, the gate pad provides an interconnect point between the cells of the device and an external lead or device. Frequently, MOSFET (IGBT) devices are interconnected to external circuitry by soldering the drain (collector) and wire bonding the gate and source (gate and emitter) to other interconnects. Other solderable MOSFET devices, such as flip-chip devices, have been configured to allow for drain, source and gate interconnects to be achieved with a solder connection. Similarly, IGBT devices have been constructed such that collector, gate and emitter connections are made through a solder connection.
In semiconductor devices that have implemented solder connections, at least one such device has located a gate pad in a corner of the device. With reference to
As such, it would be desirable to develop a technique that reliably allows high current and high power devices to achieve relatively uniform current flow through the device during switching events.
According to the present invention, a semiconductor device includes a device body, a gate pad and a gate signal distribution runner. The device body includes a plurality of parallel cells and the gate pad is located on a top surface of the device body adjacent a corner of the device body. The gate signal distribution runner includes a peripheral gate signal distribution runner extending around the periphery of the device body from the gate pad and a diagonal gate signal distribution runner extending diagonally across the device body from the gate pad. The gate signal distribution runner provides a gate signal to a gate of each of the plurality of parallel cells.
These and other features, advantages and objects of the present invention will be further understood and appreciated by those skilled in the art by reference to the following specification, claims and appended drawings.
The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
According to various embodiments of the present invention, techniques are disclosed that allow a gate signal to be more uniformly provided to parallel cells of a semiconductor device, e.g., a metal-oxide semiconductor field-effect device (MOSFET) or an insulated-gate bipolar transistor (IGBT). According to the present invention, a diagonal gate signal distribution runner, that emanates from a corner of the device (where the gate pad is located) to an opposite corner of the device (traversing the triangle hypotenuse), is employed to uniformly distribute a gate signal to a gate region of each of a plurality of parallel cells. According to another embodiment of the present invention, for higher frequency MOSFET and IGBT applications where uniform gate impedance and propagation is even more desirable, additional gate signal distribution runners are added perpendicular to the diagonal gate signal distribution runner. It should be appreciated that the additional gate runners tend to further minimize gate impedance and allow for more uniform gate signal propagation across the device. For the sake of clarity, the source and drain connections are not shown in
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Accordingly, a number of semiconductor devices have been described herein, which, in general, include a device body including a plurality of parallel cells, with a gate pad located on a top surface of the device body adjacent a corner of the device body. The devices further include a gate signal distribution runner having a peripheral gate signal distribution runner extending around a periphery of the device body from the gate pad and a diagonal gate signal distribution runner extending diagonally across the device body from the gate pad. The gate signal distribution runner provides a gate signal to a gate of each of the plurality of parallel cells in a uniform manner, thus, providing a semiconductor device that has more consistent propagation delays, which is especially advantageous in high frequency and/or high power applications.
Accordingly, a number of semiconductor devices have been described herein that exhibit uniform current flow through the devices during switching event. Such semiconductor devices are particularly useful in environments where high current and high power devices are increasingly utilized.
The above description is considered that of the preferred embodiments only. Modifications of the invention will occur to those skilled in the art and to those who make or use the invention. Therefore, it is understood that the embodiments shown in the drawings and described above are merely for illustrative purposes and not intended to limit the scope of the invention, which is defined by the following claims as interpreted according to the principles of patent law, including the doctrine of equivalents.
