Claims
- 1. A semiconductor device comprising:
- a semiconductor substrate;
- an emitter region of a first conductivity type formed on said semiconductor substrate;
- a base region of a second conductivity type formed to surround said emitter region;
- a collector region of the first conductivity type including a low impurity concentration collector portion and a high impurity concentration collector portion;
- a high impurity concentration collector electrode connecting region of the first conductivity type formed on and in contact with a part of said high impurity concentration collector portion;
- wherein said high impurity concentration collector portion includes a buried layer under said base region, said low impurity concentration collector portion includes a first low impurity concentration portion which is underneath said emitter region to connect said base region to said high impurity concentration collector portion and a second low impurity concentration portion surrounding said base region and said first low impurity concentration portion to isolate said base region and said first low impurity concentration portion from regions surrounding said collector region, with the impurity concentration of said first low impurity concentration portion being lower than that of said second low impurity concentration portion.
- 2. A semiconductor device according to claim 1, further comprising a first conductivity type region formed in a MOS transistor forming area on said semiconductor substrate;
- source and drain regions of the second conductivity type separately formed on said first conductivity type region; and
- an electrode formed on said first conductivity type region which lies between said source and drain regions;
- wherein said emitter region formed said low impurity concentration collector region and in said first conductivity type region have the same impurity concentration.
- 3. A semiconductor device comprising:
- a semiconductor substrate;
- an emitter region of a first conductivity type formed on said semiconductor substrate;
- a base region of a second conductivity type formed to surround said emitter region;
- a collector region of the first conductivity type including a low impurity concentration collector portion and a high impurity concentration collector portion;
- a high impurity concentration collector electrode connecting region of the first conductivity type formed on and in contact with a part of said high impurity concentration collector portion;
- a first well region of the second conductivity type formed in contact with said low impurity concentration collector portion;
- a second well region of the second conductivity type formed on said semiconductor substrate;
- a third well region of the first conductivity type formed on said semiconductor substrate;
- a first MOS transistor of the first conductivity type formed in said second well region; and
- a second MOS transistor of the second conductivity type formed in said third well region;
- wherein said high impurity concentration collector portion includes a buried layer under said base region, said low impurity concentration collector portion includes a first low impurity concentration portion which is underneath said emitter region to connect said base region to said high impurity concentration collector portion and a second low impurity concentration portion surrounding said base region and said first low impurity concentration portion to isolate said base region and said first low impurity concentration portion from regions surrounding said collector region, with the impurity concentration of said first low impurity concentration portion being lower than that of said second low impurity concentration portion.
- 4. A semiconductor device comprising:
- a semiconductor substrate;
- an emitter region of a first conductivity type formed on said semiconductor substrate;
- a base region of a second conductivity type formed to surround said emitter region;
- a collector region of the first conductivity type including a low impurity concentration collector portion and a high impurity concentration collector portion;
- a high impurity concentration collector electrode connecting region of the first conductivity type formed on and in contact with a part of said high impurity concentration collector portion;
- wherein said high impurity concentration collector portion includes a buried layer under said base region, said low impurity concentration collector portion includes a first low impurity concentration portion which is directly below said base region and between said base region and said high impurity concentration collector portion to connect said base region to said high impurity concentration collector portion, and a second low impurity concentration portion out of contact with said base region and surrounding said base region and said first low impurity concentration portion to isolate said base region and said first low impurity concentration portion from regions surrounding said collector region, with the impurity concentration of said first low impurity concentration portion being lower than that of said second low impurity concentration portion.
- 5. A semiconductor device according to claim 4, further comprising a first conductivity type region formed in a MOS transistor forming area on said semiconductor substrate;
- source and drain regions of the second conductivity type separately formed on said first conductivity type region; and
- an electrode formed on said first conductivity type region which lies between said source and drain regions;
- wherein said emitter region is formed in said low impurity concentration collector portion and has the same impurity concentration as said first low impurity concentration portion.
- 6. A semiconductor device comprising:
- a semiconductor substrate;
- an emitter region of a first conductivity type formed on said semiconductor substrate;
- a base region of a second conductivity type formed to surround said emitter region;
- a collector region of the first conductivity type including a low impurity concentration collector portion and a high impurity concentration collector portion;
- a high impurity concentration collector electrode connecting region of the first conductivity type formed on and in contact with a part of said high impurity concentration collector portion;
- wherein said high impurity concentration collector portion includes a buried layer under said base region, said low impurity concentration collector portion includes a first low impurity concentration portion which is directly below said base region and between said base region and said high impurity concentration collector portion to connect said base region to said high impurity concentration collection portion and a second low impurity concentration portion surrounding and out of contact with said base region to isolate said base region and said first low impurity concentration portion from regions surrounding said collector region, with the impurity concentration of said first low impurity concentration portion being lower than that of said second low impurity concentration portion.
- 7. A semiconductor device of claim 6, further comprising a first conductivity type region formed in a MOS transistor forming area on said semiconductor substrate;
- source and drain regions of the second conductivity type separately formed on said first conductivity type region;
- an electrode formed on said first conductivity type region which lies between said source and drain regions;
- device-isolation insulating film; and
- field inversion preventing ion-implemented region.
Priority Claims (1)
Number |
Date |
Country |
Kind |
1-121569 |
May 1989 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/523,892, filed May 16, 1990, now abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0219641 |
Apr 1987 |
EPX |
1237712 |
Jun 1971 |
GBX |
1280022 |
Jul 1972 |
GBX |
Non-Patent Literature Citations (3)
Entry |
Muller et al., Device Elec. for IC's, 1986, pp. 193-202. |
Patent Abstracts of Japan, vol. 13, No. 46 (E-711)[3394] Feb. 2, 1989; Japanese Patent Document No. 63-240058, dated Oct. 5, 1988, NEC Corp. |
IBM Technical Disclosure Bulletin, vol. 13, No. 7, Dec. 1970, p. 1981; "Symmetrical Transistor Structure", Davidson et al. |
Continuations (1)
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Number |
Date |
Country |
Parent |
523892 |
May 1990 |
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