Patent Application
20110204517
The present description relates, in general, to vias and, more specifically, to vias having two or more conductive materials therein.
Many devices currently use chip packages that have two or more chips (e.g., a processor chip and a memory chip) that are stacked. Some conventional designs use Through Silicon Vias (TSVs) to couple the chips together. As their name suggests, TSVs are generally substantially vertical interconnects used to make electrical connections through a semiconductor. TSVs can be used to couple devices within the same die or in different but adjacent (e.g., stacked) dies. Ideally, a via should have low resistance since it carries signals between the chips. Many conventional TSVs use copper for a conductor because of its low resistance. However, the use of copper presents some challenges.
One challenge is that some conventional TSV fabrication techniques use a barrier/seed deposition process to couple the copper material to the inside surface of the vias. The barrier/seed deposition process is usually performed with Physical Vapor Deposition (PVD), which can be a high-cost and technically challenging process.
Another challenge with using copper is that the Coefficient of Thermal Expansion (CTE) of copper is around sixteen ppm per degree Celsius. By contrast, silicon (a common material for semiconductor substrates) has a CTE of around three ppm per degree Celsius; thus, there is a factor of five or six difference between the CTEs of the two materials. When a chip is subject to thermal cycling, the copper will bend more than silicon bends so that the copper material in a via may “pop up” affecting material above the via. In some instances, thermal changes in the shape of copper materials of vias have caused delamination with low-K dielectric layers, and even breaking metal lines that couple to vias. Moreover, delamination occurs between the copper in the vias and silicon dioxide liners in the vias.
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One proposal to avoid the disadvantages of copper is to use a different material, such as tungsten. Tungsten has a lower CTE than does copper, and the CTE of tungsten is closer to that of silicon, but there is a penalty for using tungsten. Specifically, the resistance of tungsten is higher than that of copper. Also, it can be difficult to form a larger diameter via using tungsten because tungsten is usually deposited with a CVD plasma process. Using CVD plasma processes, there is a maximum thickness of about one micron, which can be inadequate for a six micron via.
According to one embodiment, a semiconductor die includes a via within a substrate material of the semiconductor die. The via includes a first conductive material having a first Coefficient of Thermal Expansion (CTE) and a second conductive material between the first conductive material and the substrate material of the semiconductor die. The second conductive material has a second CTE between the first CTE and a CTE of the substrate material of the semiconductor die.
According to another embodiment, a method for fabricating a via within a semiconductor die includes removing semiconductor material to create a hole through a substrate of the semiconductor die. The method further includes depositing a first conductive material, having a first coefficient of thermal expansion (CTE), within the hole and depositing a second conductive material, having a second CTE, over at least a portion of the first conductive material. The first CTE is between the second CTE and a CTE of the substrate of the semiconductor die.
According to another embodiment, a method for fabricating a via within a semiconductor die includes the step of removing semiconductor material to create a hole through a substrate of the semiconductor die. The method further includes the steps of depositing a first conductive material, having a first coefficient of thermal expansion (CTE), within the hole and depositing a second conductive material, having a second CTE, over at least a portion of the first conductive material. The first CTE is between the second CTE and a CTE of the substrate of the semiconductor die.
According to yet another embodiment, a semiconductor die has a via within a substrate material of the semiconductor die. The via includes first means for conducting electrical signals having a first Coefficient of Thermal Expansion (CTE) and second means for conducting electrical signals between the first conducting means and the substrate material of the semiconductor die. The second conducting means has a second CTE between the first CTE and a CTE of the material of the semiconductor die.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.
The TSV 210 includes two conductive materials. One conductive material is copper 211, and the other conductive material is a buffer metal 212, which is disposed between the copper 211 and the substrate 201. The buffer metal 212 has a CTE between that of the substrate 201 (i.e., about 3 ppm per degree Celsius for silicon) and that of copper (i.e., 16 ppm per degree Celsius). Various suitable buffer materials include, but are not limited to, tungsten (CTE of about 4.5 ppm per degree Celsius) and nickel (CTE of about thirteen ppm per degree Celsius).
The presence of the buffer metal 212 can provide several structural enhancements. For instance, the stress at the buffer/liner (e.g., tungsten/silicon dioxide) interface and the stress at the filler/buffer (e.g., copper/tungsten) will be reduced due to the intermediate CTE of the buffer metal 212. Also, the pushing force applied by the TSV 210 on items above/below it can be reduced. Both enhancements are explained in more detail with respect to
The TSV 300 includes features that are different than features of the all-copper TSV 100 of
Dies according to various embodiments may be fabricated in any of a variety of ways. In one example, a technique called “via first” is performed. The via first method involves forming the TSVs in a substrate before other fabrication of circuitry (e.g., transistors) occurs. A pattern of vias is etched or drilled into a fraction of the depth of the base substrate. The vias are then filled with a buffer metal and another conductive material, such as copper. Circuit fabrication follows, which can include high-temperature processes to properly dope the semiconductor material. The back side of the substrate containing the TSVs is ground down to expose the TSVs.
In a “via last” technique, circuitry fabrication takes place before the TSVs are formed. The circuitry contains interconnect pads that will be coupling points for the TSVs. TSVs are created by either etching or drilling into the pad through the depth of the substrate or etching or drilling from the back side of the substrate to the pad. The TSV is then filled with a buffer metal and another conductive material.
Using a via first technique, the front end of the line processing is performed first, then the vias are fabricated, followed by the back end of the line processing. Using the via last approach, the front end of the line processing is performed first, then back end of the line processing is performed, then vias are fabricated through the stack. Another approach is referred to as “via middle,” in which TSVs are formed after the circuitry is formed but before back end of the line processing is performed. An advantage of via middle and via last techniques is that the TSVs in such techniques are not exposed to the extreme temperatures of the doping process. Various embodiments are not limited to any particular method for fabricating TSVs and semiconductor devices, as any method now known or later developed to fabricate TSVs can be used.
In block 402, a first conductive material is deposited within the hole. Various techniques can be used, including PVD techniques and CVD techniques. In embodiments that use tungsten for a buffer metal, plasma CVD may be used, though the scope of embodiments is not limited to tungsten nor to any particular technique for deposition of the first conductive material.
In block 403, a second conductive material is deposited over at least a portion of the first conductive material. In this example, in block 403, the second conductive material is deposited within the space on the inner surface of the first conductive material. Examples of a second conductive material include, but are not limited, to copper and silver. In embodiments that use copper, block 403 may include Electrochemical Plating (ECP) processes to deposit the copper, though the scope of embodiments is not limited to any particular process. In some embodiments, block 403 may include filling in the remainder of the via with the second conductive material.
While the method 400 is shown as a series of discrete blocks, the disclosure is not so limited. Various embodiments may add, omit, modify, or rearrange the actions of the blocks 401-403. For instance, any method for fabricating dies can be used, including, e.g., via first, via last, and via middle techniques. Furthermore, some embodiments may include integrating the semiconductor die into a chip package with another die and installing the chip package into a larger device, such as a device shown in
Moreover, while the examples above show two conductive materials used in a TSV, the scope of embodiments is not so limited. It should be noted that multiple, different layers of buffer metals can be used in other embodiments. Thus, in some embodiments, block 402 may include depositing two or more different buffer materials in the TSV.
Various embodiments may provide one or more advantages over conventional designs that use vias with only a single conductive material. For instance, as mentioned above, various embodiments ameliorate the temperature-induced deformation of vias, thereby reducing the incidence of delamination at interfaces and metal line cracking.
Furthermore, in some embodiments the barrier/seed deposition processes of conventional techniques can be omitted. Specifically, the buffer metal layers themselves can sometimes be used as a barrier and seed. Also, the buffer metal layer deposition can sometimes be performed by various CVD processes (depending on the particular metals used for the buffer layers), which have a lower cost and better step coverage than PVD processes for conventional designs. Improved step coverage performance can facilitate the use of smaller vias, such as those of two microns or less in diameter.
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The methodologies described herein may be implemented by various components depending upon the application. For example, these methodologies may be implemented in hardware, firmware, software, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, or a combination thereof.
For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. Any machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit. As used herein the term “memory” refers to any type of long term, short term, volatile, nonvolatile, or other memory and is not to be limited to any particular type of memory or number of memories, or type of media upon which memory is stored.
If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
