BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment of the present invention.
FIG. 1B is a cross-sectional view of the semiconductor device taken along the line Ib-Ib in FIG. 1A.
FIG. 1C is a cross-sectional view of the semiconductor device taken along the line Ic-Ic in FIG. 1A.
FIG. 1D is a cross-sectional view of the semiconductor device taken along the line Id-Id in FIG. 1A.
FIG. 2 is a graph indicating relationship between the extended width of a channel region and off-leakage characteristics.
FIG. 3 is a plan view illustrating an exemplary layout in which a single common gate electrode is disposed over a plurality of device active portions.
FIG. 4 is a plan view for explaining the base end width of a protruding region.
FIG. 5 is a plan view for explaining the shape of the protruding region.
FIG. 6 is another plan view for explaining the shape of the protruding region.
FIG. 7 is another plan view for explaining the shape of the protruding region.
FIG. 8 is a plan view for explaining the shape of source and drain regions.
FIG. 9 is another plan view for explaining the shape of the source and drain regions.
FIG. 10 is a plan view for explaining an extended region.
FIG. 11 is another plan view for explaining the extended region.
FIG. 12 is a plan view for explaining recessed regions.
FIG. 13 is a graph for explaining hump characteristics.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
First Embodiment
FIG. 1A is a plan view illustrating a semiconductor device according to a first embodiment of the present invention. FIGS. 1B, 1C, and 1D are cross-sectional views of the semiconductor device taken along the lines Ib-Ib, Ic-Ic, and Id-Id, respectively, in FIG. 1A.
The semiconductor device includes a semiconductor substrate 100, a device active portion 101, a device isolation portion 102, a gate insulating film 103, and a gate electrode 104.
The device active portion 101 is formed in the principal surface of the semiconductor substrate 100. The device isolation portion 102, which is a STI (shallow trench isolation), for example, is formed in the principal surface of the semiconductor substrate 100 so as to surround the periphery of the device active portion 101. The gate electrode 104 is stacked over the device active portion 101 with the gate insulating film 103 interposed therebetween.
The device active portion 101 includes a source region 105, a drain region 106, and a channel region 107. The source region 105 and the drain region 106 are formed so as to be opposite each other in the gate length direction (the direction of length of the gate electrode 104). The channel region 107 is formed between the source region 105 and the drain region 106. The gate width of the gate electrode 104 is greater than the length of the channel region 107 in the gate width direction (in the direction of width of the gate electrode 104), and both ends of the gate electrode 104 extend over the device isolation portion 102.
The channel region 107 is located inwardly of the gate electrode 104, when viewed in the stacking direction. The channel region 107 includes a central region 107a and protruding regions 107b and 107c. When viewed in the stacking direction, the central region 107a has a rectangular shape extending from a side end of the source region 105 to a side end of the drain region 106 in the gate length direction. When viewed in the stacking direction, the protruding region 107b protrudes from one side end of the central region 107a in the gate width direction, while the protruding region 107c protrudes from the other side end of the central region 107a in the gate width direction.
The source region 105 and the drain region 106 have the same conductivity type. The conductivity type of the channel region 107 is opposite to that of the source and drain regions 105 and 106. For example, when the source and drain regions 105 and 106 are n-type semiconductor layers, the channel region 107 is a p-type semiconductor layer.
Although not shown, wiring is formed in the gate electrode 104, the source region 105, and the drain region 106 via contacts. This wiring allows the semiconductor device shown in FIG. 1A to operate as a transistor in a semiconductor integrated circuit.
Now, a description will be made of subchannels which are formed in the channel region 107 shown in FIG. 1. The subchannels are channels having a lower threshold voltage than a channel formed in the central region 107a and occurring in parts of the channel region 107 located near the boundary with the device isolation portion 102.
In the channel region 107 shown in FIG. 1, one of the subchannels is formed along the periphery of the protruding region 107b. The length of the subchannel in the protruding region 107b thus becomes greater as compared with a case in which the protruding region 107b is not formed (i.e., in a case in which one side end of the central region 107a is in contact with the device isolation portion 102). This greater length causes the resistance of the subchannel to increase to thereby reduce the amount of electric charge passing thorough the subchannel, as compared with the case where the protruding region 107b is not formed. The same holds true for the protruding region 107c, and the amount of electric charge passing thorough the subchannel therein is reduced. It is thus possible to reduce off-leakage current.
FIG. 2 shows results of 3-D device simulation of relationship between the extended width of the channel region 107 (i.e., the protrusion length of the protruding regions 107b and 107c) and the off-leakage current. The simulation was performed for a transistor having a gate length of 0.1 μm and a gate width (a source width, a drain width) of 0.16 μm. In the simulation results shown in FIG. 2, when the protrusion length of the protruding regions is equal to or greater than 10 nm, the off-leakage current is substantially reduced. The lower limit of the protrusion length of the protruding regions varies depending on the gate length, the gate width, and other parameters in the semiconductor device.
As described above, hump characteristics are suppressed. Furthermore, when viewed in the stacking direction, the channel region is located inwardly of the gate electrode. Thus, unlike in the conventional case (shown in Patent Document 1), it is not necessary to cover and protect a specific region, allowing the semiconductor device to be fabricated in an easier manner as compared with the conventional case. That is, in forming the device isolation portion 102, it is sufficient to pattern the device active portion in such a manner that the protruding regions can be formed in a later step, thereby eliminating the need for adding another step (e.g., a covering step for forming a semiconductor region). To be specific, it is sufficient to pattern the device active portion in such a manner that, in the gate width direction, the length of the part of the device active portion that is to be the channel region is greater than the length of the parts thereof that are to be the source and drain regions 105 and 106 and is smaller than the length (the gate width) of the gate electrode that is to be formed later.
Also, in the conventional case (shown in Patent Document 1), since semiconductor regions are formed in parts of the semiconductor substrate that correspond in position to both ends of the gate electrode, there are many restrictions imposed on the layout. For example, in a layout for an inverter circuit or the like, a single common gate electrode is disposed across a plurality of transistors (device active portions). In such a layout, it is not possible to form semiconductor regions for the respective device active portions as in the conventional case. In contrast, as shown in FIG. 3, in the semiconductor device of this embodiment, a single common gate electrode can be disposed over a plurality of device active portions for formation of an inverter circuit, and the number of restrictions imposed on the layout is thus reduced as compared with the conventional case.
(Modified Examples of the Device Active Portion)
Next, with reference to FIGS. 4 to 12, modified examples of the device active portion 101 shown in FIG. 1 will be described in detail.
(1) The Base End Width of the Protruding Region
As shown in FIG. 4, the width X of the base end of the protruding region 107b may be smaller than the width Y of one side end of the central region 107a. That is, if the base end width of the protruding region is equal to or smaller than the width of the one side end of the central region, off-leakage current can be reduced.
(2) Shape of the Protruding Region
As shown in FIG. 5, the protruding region 107b may have a shape in which the protrusion width thereof is gradually reduced in the direction going from the base end thereof to the distal end thereof. Alternatively, as shown in FIG. 6, the protruding region 107b may have an opposite shape in which the protrusion width thereof is gradually increased in the direction going from the base end thereof to the distal end thereof. Furthermore, the distal end portion of the protruding region 107b may be expanded as shown in FIG. 7. That is, the protruding region 107b may have a shape in which the protrusion width thereof continuously changes in the direction in which the protruding region 107b protrudes. It should be noted that the protruding region 107b typically has a rounded shape as shown in FIG. 5.
(3) Shape of the Side End Portions of the Source and Drain Regions.
As shown in FIG. 8, the source region 105 may be formed so that the width of a side end portion thereof is gradually increased in the direction toward the central region 107a. Also, as shown in FIG. 9, both ends of the side end portion of the source region 105 that is in contact with the channel region (the central region 107a and the protruding regions 107b and 107c) may be rounded. The same holds true for the drain region 106.
(4) Extended Region
As shown in FIG. 10, the device active portion 101 may includes an extended region 108 which extends from the edge of the distal end portion of the protruding region 107c. That is, part of the channel region may extend beyond the gate electrode 104. The extended region 108 is a part of the channel region that extends outwardly of the gate electrode 104 when viewed in the stacking direction. The conductivity type of the extended region 108 may be the same as or different from that of the protruding region 107c. When the conductivity type of the extended region 108 is the same as that of the protruding region 107c, the extended region 108 may be used as a substrate contact region.
If the extended region 108 is formed in a different position determined with consideration, the layout shown in FIG. 3 can also be realized. For example, as in the device active portion 101 shown in the left-hand part of FIG. 3, if the end portion of the gate electrode 104 is not present over the protruding region 107c, the extended region 108 may be formed as shown in FIG. 11.
(5) Recessed Regions
As shown in FIG. 12, instead of the protruding regions, recessed regions 201b and 201c may be formed at both ends of the central region 107a. The recessed region 201b recesses from one side end of the central region 107a toward the inside of the central region in the gate width direction. The recessed region 201c recesses from the other side end of the central region toward the inside of the central region in the gate width direction. In this case, since a subchannel is formed along the periphery of the recessed region 201b, off-leakage current can be reduced further as compared with cases in which the recessed region 201b is not formed. The same holds true for the recessed region 201c.
In the above description, if at least either the protruding region 107b or 107c is formed, the effect of reducing off-leakage current is achieved. Likewise, if at least either the recessed region 201b or 201c is formed, the effect of reducing off-leakage current is achieved.
Furthermore, typical conventional hump-prevention methods, such as a process for rounding the cross-sectional shape of the boundary portion between the STI and the channel region, and a process for introducing impurities into the side faces of the trenches when the STI is formed, may be used together with the techniques described above.
The semiconductor device according to the present invention is effective in suppressing hump characteristics and reducing off-leakage current to thereby lower the circuit's power consumption.
Patent Application
20070278613
