SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is provided with test-subject circuit 1, test-irrelevant circuit 2, first pads used for the test-subject circuit, and second pads used for the test-irrelevant circuit. The first pads include a plurality of divided pad portions while each of the second pads is provided with a single pad portion.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the present invention and many of its attendant advantages will be readily obtained as the same becomes better understood by reference to the following detailed descriptions when considered in connection with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a semiconductor device in accordance with an embodiment of the present invention;

FIG. 2 is a block diagram of power source pads and test-subject circuits in accordance with the embodiment of the present invention;

FIG. 3 is a block diagram of test pads and test-subject circuits in accordance with the embodiment of the present invention;

FIG. 4 is a block diagram of test output pads and test-subject circuits in accordance with the embodiment of the present invention;

FIG. 5 is a block diagram of test input pads and test-subject circuits in accordance with the embodiment of the present invention; and

FIG. 6 is a block diagram of pads connected to a test-irrelevant circuit in accordance with the embodiment of the present invention.

Claims

1. A semiconductor device comprising: a test-subject circuit;a test-irrelevant circuit;first pads used for the test-subject circuit; andsecond pads used for the test-irrelevant circuit, wherein the first pads include a plurality of divided pad portions, and each of the second pads is provided with a single pad portion.

2. A semiconductor device according to claim 1, wherein the divided pad portions include input pad portions supplied with a reset signal, and test input pad portions supplied with test control signals to determine test modes.

3. A semiconductor device according to claim 2, further comprising a test control circuit, wherein the test control signals is input to the test control circuit to generate test signals indicative of test modes.

4. A semiconductor device according to claim 1, wherein the first pads include at least input-output pads provided with a plurality of pad portions.