Semiconductor device

Abstract

There is provided a semiconductor device including: plural macros each having plural normal blocks and a redundant block to be used as a replacement for a normal block; a first replacement information storage unit storing first replacement macro information to designate a macro to be subjected to the replacement out of the plural macros and first replacement block information to designate a normal block to be subjected to the replacement; a first transmission line serially connecting the plural macros; and a replacement information transmission circuit transmitting replacement information to the designated normal block in the designated macro via the first transmission line based on the first replacement macro information and the first replacement block information.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a configuration example of fuse circuits and a replacement information transmission circuit;

FIG. 3 is a timing chart showing a test method using a test circuit;

FIG. 4 is a diagram showing a configuration example of a semiconductor device according to a second embodiment of the present invention; and

FIG. 5 is a block diagram of a semiconductor device described in Patent Document 1.

Claims

1. A semiconductor device, comprising: plural macros each including plural normal blocks each composed of a circuit having some function and a redundant block having a same function as the normal block and, when a defect occurs in any of the normal blocks, used as a replacement for the normal block where the defect occurs;a first replacement information storage unit storing first replacement macro information to designate a macro to be subjected to the replacement out of the plural macros and first replacement block information to designate a normal block to be replaced with the redundant block out of the plural normal blocks in the designated macro;a first transmission line serially connecting the plural macros; anda replacement information transmission circuit transmitting replacement information to the designated normal block in the designated macro via said first transmission line based on the first replacement macro information and the first replacement block information stored in said first replacement information storage unit.

2. The semiconductor device according to claim 1, wherein the plural normal blocks in the macro are serially connected by said first transmission line.

3. The semiconductor device according to claim 1, wherein said replacement information transmission circuit includes plural flip-flops provided corresponding to the plural normal blocks in the plural macros, andthe plural flip-flops are serially connected by said first transmission line and serially transmit the replacement information.

4. The semiconductor device according to claim 1, wherein said first replacement information storage unit includes a fuse to store the first replacement macro information and the first replacement block information.

5. The semiconductor device according to claim 1, further comprising a second transmission line, whereinthe plural macros include plural first macros and plural second macros,said first transmission line serially connects the plural first macros,said second transmission line is connected in parallel to said first transmission line and serially connects the plural second macros, andsaid replacement information transmission circuit transmits the replacement information in parallel to the normal blocks in the first and second macros via said first and second transmission lines based on the first replacement macro information and the first replacement block information stored in said first replacement information storage unit.

6. The semiconductor device according to claim 1, further comprising a second replacement information storage unit storing second replacement macro information to designate a macro to be subjected to the replacement out of the plural macros and second replacement block information to designate a normal block to be replaced with the redundant block out of the plural normal blocks in the designated macro, whereinsaid replacement information transmission circuit transmits the replacement information to the designated two normal blocks in the designated two macros via said first transmission line based on the first replacement macro information, the first replacement block information, the second replacement macro information, and the second replacement block information.

7. The semiconductor device according to claim 5, further comprising a test read circuit storing an output signal of the first macro in synchronization with a first clock signal and storing an output signal of the second macro in synchronization with a second clock signal having a different phase from the first clock signal.

8. The semiconductor device according to claim 1, wherein the normal block and the redundant block each include a memory cell array to store data.

9. The semiconductor device according to claim 5, further comprising a second replacement information storage unit storing second replacement macro information to designate a macro to be subjected to the replacement out of the plural macros and second replacement block information to designate a normal block to be replaced with the redundant block out of the plural blocks in the designated macro, whereinsaid replacement information transmission circuit transmits the replacement information to the designated two normal blocks in the designated two macros via said first transmission line based on the first replacement macro information, the first replacement block information, the second replacement macro information, and the second replacement block information.

10. The semiconductor device according to claim 5, wherein said first replacement information storage unit includes a fuse to store the first replacement macro information and the first replacement block information.

11. The semiconductor device according to claim 6, wherein said second replacement information storage unit includes a fuse to store the second replacement macro information and the second replacement block information.