Internal storage of test result, quality data, chip identification, repair information

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G11C2029/4402

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G11C2029/4402Internal storage of test result, quality data, chip identification, repair information

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Patents Grantslast 30 patents

Information Patent Grant
Trim setting determination for a memory device
- Patent number 12,367,942
- Issue date Jul 22, 2025
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device including sense amplifying circuit
- Patent number 12,315,579
- Issue date May 27, 2025
- SK Hynix Inc.
- Yeonsu Jang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for real-time repairing of memory failures caused during op...
- Patent number 12,254,940
- Issue date Mar 18, 2025
- Samsung Electronics Co., Ltd.
- Yoonyul Yoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device, memory system and method of controlling semic...
- Patent number 12,243,606
- Issue date Mar 4, 2025
- AP Memory Technology Corporation
- Hsin-Nan Chueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cryptographic system memory management
- Patent number 12,238,221
- Issue date Feb 25, 2025
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM retention test method for dynamic error correction
- Patent number 12,190,974
- Issue date Jan 7, 2025
- RAMBUS INC.
- Ely Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory test system and memory test method
- Patent number 12,190,977
- Issue date Jan 7, 2025
- NANYA TECHNOLOGY CORPORATION
- Cheng-Ting Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test system and memory test method
- Patent number 12,190,978
- Issue date Jan 7, 2025
- NANYA TECHNOLOGY CORPORATION
- Cheng-Ting Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for enabling multiple return material authoriz...
- Patent number 12,183,412
- Issue date Dec 31, 2024
- Altera Corporation
- Sankaran M. Menon
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for identifying memory devices of a semicon...
- Patent number 12,184,280
- Issue date Dec 31, 2024
- Dean Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing memory array operational information in non-volatile subarrays
- Patent number 12,158,826
- Issue date Dec 3, 2024
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAM test with parity error detection and handling
- Patent number 12,130,700
- Issue date Oct 29, 2024
- Hamilton Sundstrand Corporation
- Qiuming Leng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory repair method and apparatus based on error code tracking
- Patent number 12,111,723
- Issue date Oct 8, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-stage voltage calibration upon power-up of memory device
- Patent number 12,073,866
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Steven Michael Kientz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and data processing system including the same
- Patent number 12,056,027
- Issue date Aug 6, 2024
- SK Hynix Inc.
- Eung-Bo Shim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and method for controlling nonvolatile memory during...
- Patent number 12,038,834
- Issue date Jul 16, 2024
- Kioxia Corporation
- Shinichi Kanno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer circuit with adaptive repair capability
- Patent number 12,040,035
- Issue date Jul 16, 2024
- RAMBUS INC.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Grant
Authenticity and yield by reading defective cells
- Patent number 12,027,224
- Issue date Jul 2, 2024
- International Business Machines Corporation
- Julien Frougier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with dynamic processing level calibration
- Patent number 12,001,286
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Larry J. Koudele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indicating a blocked repair operation
- Patent number 11,948,655
- Issue date Apr 2, 2024
- Micron Technology, Inc.
- Seth A. Eichmeyer
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal timing alignment based on a common data strobe in memory dev...
- Patent number 11,935,578
- Issue date Mar 19, 2024
- III Holdings 2, LLC
- Michael C. Stephens
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module having open-drain output for error reporting and for...
- Patent number 11,880,319
- Issue date Jan 23, 2024
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Centrally logging and aggregating miscompares on chip during memory...
- Patent number 11,869,616
- Issue date Jan 9, 2024
- Cypress Semiconductor Corporation
- Senwen Kan
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectable trim settings on a memory device
- Patent number 11,854,634
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reclaimable semiconductor device package and associated systems and...
- Patent number 11,854,635
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Yueping Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Undo and redo of soft post package repair
- Patent number 11,837,314
- Issue date Dec 5, 2023
- SK Hynix NAND Product Solutions Corp.
- Bill Nale
- G11 - INFORMATION STORAGE
Information Patent Grant
Trim setting determination on a memory device
- Patent number 11,836,078
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trim setting determination for a memory device
- Patent number 11,817,164
- Issue date Nov 14, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory systems including simplified BISR logic circuit
- Patent number 11,804,278
- Issue date Oct 31, 2023
- SK hynix Inc.
- Bo Ra Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
End of life performance throttling to prevent data loss
- Patent number 11,756,638
- Issue date Sep 12, 2023
- Micron Technology, Inc.
- Sebastien Andre Jean
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
- Publication number 20250201328
- Publication date Jun 19, 2025
- Rambus Inc.
- Ely Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
- Publication number 20250166719
- Publication date May 22, 2025
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICON...
- Publication number 20250150081
- Publication date May 8, 2025
- Lodestar Licensing Group LLC
- Dean Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS
- Publication number 20250130908
- Publication date Apr 24, 2025
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING
- Publication number 20250086051
- Publication date Mar 13, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICON...
- Publication number 20250070782
- Publication date Feb 27, 2025
- Lodestar Licensing Group LLC
- Dean Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Balancing throughput and response time quality of service
- Publication number 20240430323
- Publication date Dec 26, 2024
- PURE STORAGE, INC.
- Ahmad Alnafoosi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
- Publication number 20240420793
- Publication date Dec 19, 2024
- Rambus Inc.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Application
TWO-STAGE VOLTAGE CALIBRATION UPON POWER-UP OF MEMORY DEVICE
- Publication number 20240386936
- Publication date Nov 21, 2024
- Micron Technology, Inc.
- Steven Michael Kientz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME
- Publication number 20240354210
- Publication date Oct 24, 2024
- SK HYNIX INC.
- Eung-Bo SHIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH DYNAMIC PROCESSING LEVEL CALIBRATION
- Publication number 20240289226
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Larry J. Koudele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEV...
- Publication number 20240265961
- Publication date Aug 8, 2024
- III Holdings 2, LLC
- Michael C. Stephens
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE PROVIDING DISTINCT SIGNALING INTERFACES VIA AN OPEN-D...
- Publication number 20240232105
- Publication date Jul 11, 2024
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIM SETTING DETERMINATION ON A MEMORY DEVICE
- Publication number 20240211395
- Publication date Jun 27, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE
- Publication number 20240203516
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
- Publication number 20240161846
- Publication date May 16, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
- Publication number 20240127901
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Daniel S. Miller
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING...
- Publication number 20240079076
- Publication date Mar 7, 2024
- SK HYNIX INC.
- Hong Ki MOON
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
- Publication number 20240079079
- Publication date Mar 7, 2024
- Rambus Inc.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM
- Publication number 20230386597
- Publication date Nov 30, 2023
- Samsung Electronics Co., LTD
- TAEKWOON KIM
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
- Publication number 20230377668
- Publication date Nov 23, 2023
- Rambus Inc.
- Ely Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDICATING A BLOCKED REPAIR OPERATION
- Publication number 20230343409
- Publication date Oct 26, 2023
- Micron Technology, Inc.
- Seth A. Eichmeyer
- G11 - INFORMATION STORAGE
Information Patent Application
AUTHENTICITY AND YIELD BY READING DEFECTIVE CELLS
- Publication number 20230298683
- Publication date Sep 21, 2023
- International Business Machines Corporation
- Julien Frougier
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
- Publication number 20230170039
- Publication date Jun 1, 2023
- Rambus Inc.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Application
CENTRALLY LOGGING AND AGGREGATING MISCOMPARES ON CHIP DURING MEMORY...
- Publication number 20230142759
- Publication date May 11, 2023
- CYPRESS SEMICONDUCTOR CORPORATION
- Senwen Kan
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME
- Publication number 20230015404
- Publication date Jan 19, 2023
- SK HYNIX INC.
- Eung-Bo SHIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATICALLY SKIP BAD BLOCK IN CONTINUOUS READ OR SEQUENTIAL CACHE...
- Publication number 20220392562
- Publication date Dec 8, 2022
- Macronix International Co., Ltd.
- Shuo-Nan HUNG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DUTY-CYCLE SKEW MANAGEMENT
- Publication number 20220366995
- Publication date Nov 17, 2022
- Micron Technology, Inc.
- Yang Lu
- G11 - INFORMATION STORAGE
Information Patent Application
DEBUGGING MEMORY DEVICES
- Publication number 20220351799
- Publication date Nov 3, 2022
- Micron Technology, Inc.
- Junam Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEMS INCLUDING SIMPLIFIED BISR LOGIC CIRCUIT
- Publication number 20220351801
- Publication date Nov 3, 2022
- SK HYNIX INC.
- Bo Ra KIM
- G11 - INFORMATION STORAGE

Internal storage of test result, quality data, chip identification, repair information

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Trim setting determination for a memory device

Memory device including sense amplifying circuit

Methods for real-time repairing of memory failures caused during op...

Semiconductor device, memory system and method of controlling semic...

Cryptographic system memory management

DRAM retention test method for dynamic error correction

Memory test system and memory test method

Memory test system and memory test method

Method and apparatus for enabling multiple return material authoriz...

Apparatuses and methods for identifying memory devices of a semicon...

Storing memory array operational information in non-volatile subarrays

RAM test with parity error detection and handling

Memory repair method and apparatus based on error code tracking

Two-stage voltage calibration upon power-up of memory device

Memory system and data processing system including the same

Memory system and method for controlling nonvolatile memory during...

Buffer circuit with adaptive repair capability

Authenticity and yield by reading defective cells

Memory device with dynamic processing level calibration

Indicating a blocked repair operation

Signal timing alignment based on a common data strobe in memory dev...

Memory module having open-drain output for error reporting and for...

Centrally logging and aggregating miscompares on chip during memory...

Selectable trim settings on a memory device

Reclaimable semiconductor device package and associated systems and...

Undo and redo of soft post package repair

Trim setting determination on a memory device

Trim setting determination for a memory device

Memory systems including simplified BISR logic circuit

End of life performance throttling to prevent data loss

Patents Applicationslast 30 patents

DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION

TRIM SETTING DETERMINATION FOR A MEMORY DEVICE

APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICON...

STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS

MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING

APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICON...

Balancing throughput and response time quality of service

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

TWO-STAGE VOLTAGE CALIBRATION UPON POWER-UP OF MEMORY DEVICE

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME

MEMORY DEVICE WITH DYNAMIC PROCESSING LEVEL CALIBRATION

SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEV...

MEMORY MODULE PROVIDING DISTINCT SIGNALING INTERFACES VIA AN OPEN-D...

TRIM SETTING DETERMINATION ON A MEMORY DEVICE

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

TRIM SETTING DETERMINATION FOR A MEMORY DEVICE

TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION

ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING...

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION

INDICATING A BLOCKED REPAIR OPERATION

AUTHENTICITY AND YIELD BY READING DEFECTIVE CELLS

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

CENTRALLY LOGGING AND AGGREGATING MISCOMPARES ON CHIP DURING MEMORY...

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME

AUTOMATICALLY SKIP BAD BLOCK IN CONTINUOUS READ OR SEQUENTIAL CACHE...

MEMORY DUTY-CYCLE SKEW MANAGEMENT

DEBUGGING MEMORY DEVICES

MEMORY SYSTEMS INCLUDING SIMPLIFIED BISR LOGIC CIRCUIT