Patent Application
20240363695
The present disclosure relates to a semiconductor device that is useful as a power device or the like.
Gallium oxide (Ga2O3) is a transparent semiconductor that has a band gap that is as broad as 4.8 eV to 5.3 eV at a room temperature and hardly absorbs visible light and ultraviolet light. Therefore, gallium oxide is a promising material for use in optical/electronic devices and transparent electronics that operate in a deep ultraviolet ray region, in particular, and optical detectors, light emitting diodes (LEDs), and transistors based on gallium oxide (Ga2O3) have been developed in recent years. Mixed with indium or aluminum solely or in combination to form a mixed crystal, gallium oxide is controllable in terms of band gaps, constituting a very attractive family of material as InAlGaO-based semiconductors. Here, InAlGaO-based semiconductors indicate InXAlYGaZO3 (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5 to 2.5) and may be regarded as a family of materials including gallium oxide.
According to an example of the present disclosure, there is provided a semiconductor device including at least: an n type oxide semiconductor layer; a first p type oxide semiconductor layer that forms a main junction with the n type oxide semiconductor layer, and a hole supply layer, wherein the hole supply layer includes a second p type oxide semiconductor layer that is different from the first p type oxide semiconductor layer.
According to an example of the present disclosure, there is provided a semiconductor device including at least: a collector layer; a drift layer; and a well layer, the drift layer including an n type oxide semiconductor layer, the well layer including a first oxide semiconductor layer, the collector layer including a second oxide semiconductor layer that is different from the first oxide semiconductor layer and being an insulated gate bipolar transistor.
According to an example of the present disclosure, there is provided a semiconductor device including at least: an n type oxide semiconductor layer; a Schottky electrode that is provided on the n type oxide semiconductor layer; and a barrier layer that is provided in at least a part between the n type oxide semiconductor layer and the Schottky electrode, the barrier layer including a first oxide semiconductor layer and a second oxide semiconductor layer that is different from the first oxide semiconductor layer and being a junction barrier Schottky diode.
According to an example of the present disclosure, there is provided a semiconductor device including at least: a p type oxide semiconductor layer, an i type oxide semiconductor layer, and an n type oxide semiconductor layer, the p type oxide semiconductor layer including a first oxide semiconductor layer and a second oxide semiconductor layer that is different from the first oxide semiconductor layer and being a PiN diode.
Thus, in a semiconductor device of the present disclosure, it is possible to provide a semiconductor device with excellent semiconductor characteristics.
The present inventors have found that a semiconductor device that includes at least an n type oxide semiconductor layer, a first p type oxide semiconductor layer forming a main junction with the n type oxide semiconductor layer, and a hole supply layer in which the hole supply layer includes a second p type oxide semiconductor layer that is different from the first p type oxide semiconductor layer maintains a voltage withstanding property and has improved semiconductor characteristics such as an ON-state voltage.
Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the following description, the same parts and components are designated by the same reference numerals. The present embodiment includes, for example, the following disclosures.
A semiconductor device including at least: an n type oxide semiconductor layer; a first p type oxide semiconductor layer that forms a main junction with the n type oxide semiconductor layer, and a hole supply layer, wherein the hole supply layer includes a second p type oxide semiconductor layer that is different from the first p type oxide semiconductor layer.
The semiconductor device according to [Structure 1], wherein the first p type oxide semiconductor layer and the second p type oxide semiconductor layer has a different composition from each other.
The semiconductor device according to [Structure 1] or [Structure 2], wherein a band gap of the first p type oxide semiconductor layer is greater than a band gap of the second p type oxide semiconductor layer.
The semiconductor device according to any one of [Structure 1] to [Structure 3], wherein the first p type oxide semiconductor layer and the second p type oxide semiconductor layer are crystal growth layers.
The semiconductor device according to any one of [Structure 1] to [Structure 4], wherein a bottom surface of the first p type oxide semiconductor layer is located on a side closer to the n type oxide semiconductor layer in a stacking direction of the semiconductor device than a bottom surface of the second p type oxide semiconductor layer.
The semiconductor device according to any one of [Structure 1] to [Structure 5], wherein the n type oxide semiconductor layer contains, as major components, oxides of one or more metals selected from aluminum, gallium, and indium.
The semiconductor device according to any one of [Structure 1] to [Structure 6], wherein the n type oxide semiconductor layer has a corundum structure.
The semiconductor device according to any one of [Structure 1] to [Structure 7], wherein the first p type oxide semiconductor layer contains, as major components, oxides of one or more metals selected from aluminum, gallium, and indium.
The semiconductor device according to any one of [Structure 1] to [Structure 8], wherein the second p type oxide semiconductor layer contains at least oxide of Group 9 metal of the periodic table.
The semiconductor device according to [Structure 9], wherein the Group 9 metal of the periodic table includes iridium.
The semiconductor device according to [Structure 9] or [Structure 10], wherein the second p type oxide semiconductor layer further contains oxides of one or more metals selected from aluminum, gallium, and indium.
The semiconductor device according to any one of [Structure 1] to [Structure 11], wherein the first p type oxide semiconductor layer has a corundum structure.
The semiconductor device according to any one of [Structure 1] to [Structure 12], wherein the second p type oxide semiconductor layer has a corundum structure.
A semiconductor device including at least: a collector layer; a drift layer; and a well layer, the drift layer including an n type oxide semiconductor layer, the well layer including a first oxide semiconductor layer, the collector layer including a second oxide semiconductor layer that is different from the first oxide semiconductor layer and being an insulated gate bipolar transistor.
A semiconductor device including at least: an n type oxide semiconductor layer; a Schottky electrode that is provided on the n type oxide semiconductor layer; and a barrier layer that is provided in at least a part between the n type oxide semiconductor layer and the Schottky electrode, the barrier layer including a first oxide semiconductor layer and a second oxide semiconductor layer that is different from the first oxide semiconductor layer and being a junction barrier Schottky diode.
A semiconductor device including at least: a p type oxide semiconductor layer, an i type oxide semiconductor layer, and an n type oxide semiconductor layer, the p type oxide semiconductor layer including a first oxide semiconductor layer and a second oxide semiconductor layer that is different from the first oxide semiconductor layer and being a PiN diode.
The semiconductor device according to any one of [Structure 14] to [Structure 16], wherein the first oxide semiconductor layer and the second oxide semiconductor layer has a different composition from each other.
The semiconductor device according to any one of [Structure 14] to [Structure 17], wherein a band gap of the first oxide semiconductor layer is greater than a band gap of the second oxide semiconductor layer.
The semiconductor device according to any one of [Structure 14] to [Structure 18], wherein a bottom surface of the first oxide semiconductor layer is located on a side closer to the n type oxide semiconductor layer in a stacking direction of the semiconductor device than a bottom surface of the second oxide semiconductor layer.
The semiconductor device according to any one of [Structure 14] to [Structure 19], wherein hole carrier density of the second oxide semiconductor layer is greater than hole carrier density of the first oxide semiconductor layer.
A power conversion device that uses the semiconductor device according to any one of [Structure 1] to [Structure 20].
A control system that uses the semiconductor device according to any one of [Structure 1] to [Structure 20].
A semiconductor device according to an embodiment of the present disclosure includes at least: an n type oxide semiconductor layer; a first p type oxide semiconductor layer that forms a main junction with the n type oxide semiconductor layer, and a hole supply layer, and is characterized in that the hole supply layer includes a second p type oxide semiconductor layer that is different from the first p type oxide semiconductor layer.
The hole supply layer is not particularly limited as long as hole density is greater than electron density, holes are supplied from the hole supply layer to another layer (such as an n type oxide semiconductor layer) when the semiconductor device is operating (in an ON state), and the hole supply layer does not hinder the present disclosure. In a case where the semiconductor device is an insulated gate bipolar transistor (IGBT), the hole supply layer constitutes a collector layer. Also, in a case where the semiconductor device is a PiN diode, the hole supply layer constitutes at least a part of a p type semiconductor layer. In a case where the semiconductor device is a junction barrier Schottky diode (JBS), the hole supply layer constitutes at least a part of a barrier layer (such as a p type semiconductor layer) in the JBS. Furthermore, in a case where the semiconductor device is a diode-integrated MOSFET, the hole supply layer constitutes at least a part of a p well layer or a p type anode layer in the diode-integrated MOSFET. Also, the expression “different” in the embodiment of the present disclosure includes not only a case where the compositions of the first p type oxide semiconductor layer (first oxide semiconductor layer) and the second p type oxide semiconductor layer (second oxide semiconductor layer) are different but also a case where the compositions are the same while dopants are different. Note that in the embodiment of the present disclosure, the compositions of the first p type oxide semiconductor layer (first oxide semiconductor layer) and the second p type oxide semiconductor layer (second oxide semiconductor layer) is preferably different from each other. Moreover, the expression “main junction” means an interface having a rectification effect in the embodiment of the present disclosure. The main junction is preferably a PN junction in the embodiment of the present disclosure. Furthermore, the “p type” semiconductor layer in the present disclosure means a semiconductor layer in which hole density is greater than electron density and is not limited to a semiconductor layer that is able to be confirmed as being of a “p type” through hall effect measurement. In a case where the p type oxide semiconductor layer is used as a channel layer, for example, the p type oxide semiconductor layer is included in the “p type” as long as the p type oxide semiconductor layer functions as a channel at the time of voltage application.
The first p type oxide semiconductor layer and/or the first oxide semiconductor layer (hereinafter, also simply referred to as a “first p type oxide semiconductor layer”) is not particularly limited as long as the first p type oxide semiconductor layer is different from the second p type oxide semiconductor layer (second oxide semiconductor layer). In the embodiment of the present disclosure, the first p type oxide semiconductor layer preferably contains, as a major component, a first crystalline oxide semiconductor. Examples of the first crystalline oxide semiconductor include metal oxides of one kind or two or more kinds of metal selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the embodiment of the present disclosure, the first crystalline oxide semiconductor preferably contains at least one kind of metal selected from aluminum, indium, and gallium and more preferably contains at least gallium. In the embodiment of the present disclosure, it is also preferable that the first crystalline oxide semiconductor further contains at least one kind of metal selected from the Groups 6 to 10 of the periodic table. Examples of the Group 6 metal of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). In the embodiment of the present disclosure, the Group 6 metal of the periodic table is preferably chromium (Cr). Examples of the Group 7 metal of the periodic table include one kind or two or more kinds of metal or the like selected from manganese (Mn), technetium (Tc), and rhenium (Re). Examples of the Group 8 metal of the periodic table include one kind or two or more kinds of metal or the like selected from iron (Fe), ruthenium (Ru), and osmium (Os). Examples of the Group 9 metal of the periodic table include one kind or two or more kinds of metal or the like selected from cobalt (Co), rhodium (Rh), and iridium.
In the embodiment of the present disclosure, it is also preferable that the first crystalline oxide semiconductor is a mixed crystal containing at least the Group 9 metal of the periodic table and the Group 13 metal of the periodic table. In this case, the first p type oxide semiconductor layer is preferably a mixed crystal of iridium oxide and gallium oxide (for example, α-(Ir, Ga)2O3). Moreover, the first p type oxide semiconductor layer may contain a p type dopant in the embodiment of the present disclosure. Examples of the p type dopant include Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, and P. A crystal structure of the first p type oxide semiconductor layer is not particularly limited unless it interferes with the present disclosure. Examples of the crystal structure of the first p type oxide semiconductor layer include a corundum structure, a β-gallia structure, a hexagonal crystal structure (such as an ε type structure, for example), an orthorhombic crystal structure (such as a κ type structure, for example), a cubic crystal structure, and a tetragonal crystal structure. In the embodiment of the present disclosure, the first p type oxide semiconductor layer preferably has a corundum structure, a β-gallia structure, or a hexagonal crystal structure (such as an ε type structure, for example) and more preferably has a corundum structure. Also, the first p type oxide semiconductor layer is preferably a crystal growth layer (rather than a semiconductor layer formed by ion implantation) in the embodiment of the present disclosure. Note that the expression “major component” means that the first crystalline oxide semiconductor is contained preferably at an atomic ratio of equal to or greater than 50%, more preferably at an atomic ratio of equal to or greater than 70%, and yet further preferably at an atomic ratio of equal to or greater than 90%, or may be contained at an atomic ratio of 100% with respect to all components of the first p type oxide semiconductor layer. In a case where the first crystalline oxide semiconductor is gallium oxide, for example, it is only necessary for gallium oxide to be contained in the first p type oxide semiconductor layer at a proportion that the atomic ratio of gallium in all metal elements contained in the first p type oxide semiconductor layer is equal to or greater than 0.5. In this case, the atomic ratio of gallium in all the metal elements contained in the first p type oxide semiconductor layer is preferably equal to or greater than 0.7 and is more preferably equal to or greater than 0.9. Also, in a case where the first crystalline oxide semiconductor is a mixed crystal of gallium oxide and iridium oxide (for example, α-(Ir, Ga)2O3), for example, it is only necessary for the mixed crystal of gallium oxide and iridium oxide to be contained at a proportion that a total atomic ratio of gallium and iridium in all the metal elements in the first p type oxide semiconductor layer is equal to or greater than 0.5. In this case, the total atomic ratio of gallium and iridium in all the metal elements contained in the first p type oxide semiconductor layer is preferably equal to or greater than 0.7 and is more preferably equal to or greater than 0.9.
The hole supply layer is not particularly limited as long as the hole supply layer includes the second p type oxide semiconductor layer (second oxide semiconductor layer) that is different from the first p type oxide semiconductor layer (first oxide semiconductor layer). In the embodiment of the present disclosure, the second p type oxide semiconductor layer and/or the second oxide semiconductor layer (hereinafter, also simply referred to as a “second p type oxide semiconductor layer”) preferably contains a second crystalline oxide semiconductor as a major component. Examples of the second crystalline oxide semiconductor include metal oxides or the like containing one kind or two or more kinds of metal selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the embodiment of the present disclosure, the second crystalline oxide semiconductor preferably contains at least one kind of metal selected from aluminum, indium, and gallium and more preferably contains at least gallium. Moreover, it is also preferable that the second crystalline oxide semiconductor further contains at least one kind of metal selected from the Groups 6 to 10 of the periodic table in the embodiment of the present disclosure. Examples of the Group 6 metal of the periodic table include one kind or two or more kinds of metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W). In the embodiment, the Group 6 metal of the periodic table is preferably chromium (Cr). Examples of the Group 7 metal of the periodic table include one kind or two or more kinds of metal or the like selected from manganese (Mn), technetium (Tc), and rhenium (Re). Examples of the Group 8 metal of the periodic table include one kind or two or more kinds of metal or the like selected from iron (Fe), ruthenium (Ru), and osmium (Os). Examples of the Group 9 metal of the periodic table include one kind or two or more kinds of metal or the like selected from cobalt (Co), rhodium (Rh), and iridium.
In the embodiment of the present disclosure, it is also preferable that the second crystalline oxide semiconductor is a mixed crystal containing at least the Group 9 metal of the periodic table and the Group 13 metal of the periodic table. In this case, the second p type oxide semiconductor layer is preferably a mixed crystal of iridium oxide and gallium oxide (for example, α-(Ir, Ga)2O3). Moreover, the second p type oxide semiconductor layer may contain a p type dopant in the embodiment of the present disclosure. Examples of the p type dopant include Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, and P. A crystal structure of the second p type oxide semiconductor layer is not particularly limited unless it interferes with the present disclosure. Examples of the crystal structure of the second p type oxide semiconductor layer include a corundum structure, a β-gallia structure, a hexagonal crystal structure (such as an ε type structure, for example), an orthorhombic crystal structure (such as a κ type structure, for example), a cubic crystal structure, and a tetragonal crystal structure. In the embodiment of the present disclosure, the second p type oxide semiconductor layer preferably has a corundum structure, a β-gallia structure, or a hexagonal crystal structure (such as an ε type structure, for example) and more preferably has a corundum structure. Also, the second p type oxide semiconductor layer is preferably a crystal growth layer (rather than a semiconductor layer formed by ion implantation) in the embodiment of the present disclosure.
Note that the expression “major component” means that the second crystalline oxide semiconductor is contained preferably at an atomic ratio of equal to or greater than 50%, more preferably at an atomic ratio of equal to or greater than 70%, and yet further preferably at an atomic ratio of equal to or greater than 90%, or may be contained at an atomic ratio of 100% with respect to all components of the second p type oxide semiconductor layer. In a case where the second crystalline oxide semiconductor is gallium oxide, for example, it is only necessary for gallium oxide as the second crystalline oxide semiconductor to be contained in the second p type oxide semiconductor layer at a proportion that the atomic ratio of gallium in all metal elements contained in the second p type oxide semiconductor layer is equal to or greater than 0.5. In this case, the atomic ratio of gallium in all the metal elements contained in the second p type oxide semiconductor layer is preferably equal to or greater than 0.7 and is more preferably equal to or greater than 0.9. Also, in a case where the second crystalline oxide semiconductor is a mixed crystal of gallium oxide and iridium oxide (for example, α-(Ir, Ga)2O3), for example, it is only necessary for the mixed crystal of gallium oxide and iridium oxide to be contained at a proportion that a total atomic ratio of gallium and iridium in all the metal elements in the second p type oxide semiconductor layer is equal to or greater than 0.5. In this case, the total atomic ratio of gallium and iridium in all the metal elements contained in the second p type oxide semiconductor layer is preferably equal to or greater than 0.7 and is more preferably equal to or greater than 0.9. Also, in a case where the second crystalline oxide semiconductor is a mixed crystal of gallium oxide and chromium oxide (for example, α-(Cr, Ga)2O3), for example, it is only necessary for the mixed crystal of gallium oxide and chromium oxide to be contained at a proportion that a total atomic ratio of gallium and chromium in all the metal elements in the second p type oxide semiconductor layer is equal to or greater than 0.5. In this case, the total atomic ratio of gallium and chromium in all the metal elements contained in the second p type oxide semiconductor layer is preferably equal to or greater than 0.7 and is more preferably equal to or greater than 0.9.
In the embodiment of the present disclosure, a band gap of the first p type oxide semiconductor layer is preferably greater than a band gap of the second p type oxide semiconductor layer. The first p type oxide semiconductor has a band gap of equal to or greater than 3.5 eV and preferably a band gap of equal to or greater than 4.0 eV, for example. Also, the band gap of the second p type oxide semiconductor layer is equal to or greater than 2.5 eV and is preferably equal to or greater than 3.0 eV, for example. Moreover, the first p type oxide semiconductor layer and the second p type oxide semiconductor layer have different compositions in the embodiment of the present disclosure. More specifically, in a case where both the first p type oxide semiconductor layer and the second p type oxide semiconductor layer are mixed crystals of gallium oxide and iridium oxide, for example, the atomic ratio of gallium and iridium in the first p type oxide semiconductor layer and the atomic ratio of gallium and iridium in the second p type oxide semiconductor layer are preferably different from each other. Also, hole carrier density of the second p type oxide semiconductor layer is preferably greater than hole carrier density of the first p type oxide semiconductor layer in the embodiment of the present disclosure. The hole carrier density of the first p type oxide semiconductor layer is within a range of 1.0×1016/cm3 to 1.0×1018/cm3, for example. Also, the hole carrier density of the second p type oxide semiconductor layer is within a range of 5.0×1017/cm3 to 1.0 to 1020/cm3, for example. It is possible to further reduce an ON-state voltage of the semiconductor device and to further improve a voltage withstanding property by using different p type oxide semiconductor layers as described above. In the embodiment of the present disclosure, a bottom surface of the first p type oxide semiconductor layer is preferably located on the side closer to the n type oxide semiconductor layer in a stacking direction of the semiconductor device than a bottom surface of the second p type oxide semiconductor layer. With such a preferable structure, it is possible to achieve an effect of improving electrical characteristics such as an ON-state voltage without degrading a voltage withstanding property of the semiconductor device even in a case where a material with a band gap that is smaller than the band gap of the first p type oxide semiconductor layer is used as the second p type oxide semiconductor layer, for example. The thicknesses of the first p type oxide semiconductor layer and the second p type oxide semiconductor layer are not particularly limited unless they interfere with the present disclosure. The thickness of the first p type oxide semiconductor layer is preferably greater than the thickness of the second p type oxide semiconductor layer. The thickness of the first p type oxide semiconductor layer is within a range of 0.1 μm to 5.0 μm, for example. The thickness of the second p type oxide semiconductor layer is within a range of 0.01 μm to 3.0 μm, for example. Also, the first p type oxide semiconductor layer and the second p type oxide semiconductor layer are preferably crystal growth layers in the embodiment of the present disclosure. With such a preferable configuration, it is possible to more satisfactorily express functions of the first p type oxide semiconductor layer and the second p type oxide semiconductor layer in the combination with the n type oxide semiconductor layer.
The n type oxide semiconductor layer is not particularly limited as long as the n type oxide semiconductor layer is an oxide semiconductor layer with n type electrical conductivity and unless it interferes with the present disclosure. In the embodiment of the present disclosure, the n type oxide semiconductor layer preferably contains a crystalline oxide semiconductor as a major component. Examples of the crystalline oxide semiconductor include metal oxides or the like containing one kind or two or more kinds of metal selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. In the embodiment of the present disclosure, the crystalline oxide semiconductor preferably contains at least one kind of metal selected from aluminum, indium, and gallium, more preferably contains at least gallium, and is most preferably α-Ga2O3 or a mixed crystal thereof. The crystal structure of the n type oxide semiconductor layer is also not particularly limited unless it interferes with the present disclosure. Examples of the crystal structure of the n type oxide semiconductor layer include a corundum structure, a β-gallia structure, a hexagonal crystal structure (such as an ε type structure, for example), an orthorhombic crystal structure (such as a κ type structure, for example), a cubic crystal structure, and a tetragonal crystal structure. In the embodiment of the present disclosure, the n type oxide semiconductor layer preferably has a corundum structure, a β-gallia structure, or a hexagonal crystal structure (such as an ε type structure, for example) and more preferably has a corundum structure. Note that the expression “major component” means that the crystalline oxide semiconductor is contained preferably at an atomic ratio of equal to or greater than 50%, more preferably at an atomic ratio of equal to or greater than 70%, and yet further preferably at an atomic ratio of equal to or greater than 90%, or may be contained at an atomic ratio of 100% with respect to all components of the n type oxide semiconductor layer. In a case where the crystalline oxide semiconductor is gallium oxide, for example, it is only necessary for gallium oxide as the crystalline oxide semiconductor to be contained in the n type oxide semiconductor layer at a proportion that the atomic ratio of gallium in all metal elements contained in the n type oxide semiconductor layer is equal to or greater than 0.5. The atomic ratio of gallium in all the metal elements contained in the n type oxide semiconductor layer is preferably equal to or greater than 0.7 and is more preferably equal to or greater than 0.9. Also, although the thickness of the n type oxide semiconductor layer is not particularly limited and may be equal to or less than 1 μm or may be equal to or greater than 1 μm, the thickness of the n type oxide semiconductor layer is preferably equal to or greater than 5 μm and is more preferably equal to or greater than 10 μm in the embodiment of the present disclosure. Although a surface area (in a plan view) of the semiconductor film is not particularly limited and may be equal to or greater than 1 mm2 or may be equal to or less than 1 mm2, the surface area of the semiconductor film is preferably 10 mm2 to 300 mm2 and is more preferably 10 mm2 to 100 mm2. Also, although the n type oxide semiconductor layer is typically monocrystalline, the n type oxide semiconductor layer may be polycrystalline. Also, the n type oxide semiconductor layer typically includes two or more semiconductor layers. The n type oxide semiconductor layer includes at least an n+ type semiconductor layer, a drift layer (n− type semiconductor layer), a channel layer, and a source region (n+ type semiconductor layer), for example. Specific functions of the n type semiconductor layer in the semiconductor device will be described later along with explanation of drawings. Also, it is possible to appropriately set carrier density of the n type oxide semiconductor layer by adjusting the amount of doping.
The n type oxide semiconductor layer preferably contains an n type dopant. The n type dopant is not particularly limited and may be a known dopant. In the embodiment of the present disclosure, preferred examples of the n type dopant include n type dopants or the like such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium, for example, particularly in a case where the n type oxide semiconductor contains, as a major component, a crystalline oxide semiconductor containing gallium. In the embodiment of the present disclosure, the n type dopant is preferably at least one kind selected from Sn, Ge, and Si. The content of the n type dopant is preferably equal to or greater than 0.00001 at %, is more preferably 0.00001 at % to 20 at %, and is most preferably 0.00001 at % to 10 at % in the composition of the semiconductor layer. More specifically, the concentration of the n type dopant may be typically about 1×1016/cm3 to 1×1022/cm3, or the concentration of the n type dopant may be as low as about 1×1017/cm3 or less. Furthermore, according to the present disclosure, the dopant may be contained at a concentration that is as high as about 1×1020/cm3 or more.
The n type oxide semiconductor layer or the p type oxide semiconductor layer (hereinafter, also simply referred to as an “oxide semiconductor layer”, “semiconductor film”, or a “semiconductor layer”) may be formed using known means. Examples of the means for forming the semiconductor layer include a CVD method, an MOCVD method, an MOVPE method, a mist CVD method, a mist epitaxy method, an MBE method, an HVPE method, a pulse growth method, and an ALD method. In the embodiment of the present disclosure, the means for forming the semiconductor layer is preferably an MOCVD method, a mist CVD method, a mist epitaxy method, or an HVPE method and is preferably a mist CVD method or a mist epitaxy method. In the mist CVD method or the mist epitaxy method, a raw material solution is atomized (atomization process) using a mist CVD device illustrated in
In the atomization process, the raw material solution is atomized. Means for atomizing the raw material solution is not particularly limited as long as the means is able to atomize the raw material solution and may be known means, and atomization means using ultrasonic waves is preferable in the embodiment of the present disclosure. An initial speed of the atomized liquid droplets obtained using ultrasonic waves is zero, the atomized liquid droplets are preferable since they float in the air, and the atomized liquid droplets are very preferable since they are mist that is able to float in the air and is able to be transported as gas rather than being sprayed, for example, and no damage occurs due to collision energy. The liquid droplet size is not particularly limited, the liquid droplets may have a size of about several mm, and the size is preferably equal to or less than 50 μm and is more preferably 100 nm to 10 μm.
The raw material solution is able to be atomized or transformed into liquid droplets, is not particularly limited as long as the raw material solution contains a raw material capable of forming the semiconductor film, and may be an inorganic material or an organic material. In the embodiment of the present disclosure, the raw material is preferably metal or a metal compound and more preferably includes one kind or two or more kinds of metal selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.
In the embodiment of the present disclosure, it is possible to preferably use, as the raw material solution, a solution obtained by dissolving or dispersing the metal in the form of a complex or a salt in an organic solvent or water. Examples of the form of the complex include an acetylacetonato complex, a carbonyl complex, an ammine complex, and a hydride complex. Examples of the form of the salt include an organic metal salt (such as metal acetate, metal oxalate, and metal citrate, for example), a sulfurized metal salt, a nitrified metal salt, a phosphorylated metal salt, and a halogenated salt (such as a chlorinated metal salt, a brominated metal salt, and an iodized metal salt, for example).
Also, it is preferable to mix an additive such as a hydrohalic acid or an oxidant into the raw material solution. Examples of the hydrohalic acid include a hydrobromic acid, a hydrochloric acid, and hydriodic acid, and particularly, a hydrobromic acid or a hydriodic acid is preferable for a reason that it is possible to more efficiently reduce occurrence of abnormal particles. Examples of the oxidant include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, and organic peroxides such as a hydrochlorous acid (HClO), a perchloric acid, a nitric acid, ozone water, a peracetic acid, and nitrobenzene.
The raw material solution may contain a dopant. It is possible to satisfactorily perform doping by causing the dopant to be contained in the raw material solution. The dopant is not particularly limited unless it interferes with the present disclosure. Examples of the dopant include n type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium and p type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, and P. The content of the dopant is appropriately set by using a calibration curve indicating a relationship of concentration of the dopant in the raw materials with respect to desired carrier density.
A solvent of the raw material solution is not particularly limited, may be an inorganic solvent such as water, may be an organic solvent such as alcohol, or may be a mixed solvent of an inorganic solvent and an organic solvent. In the embodiment of the present disclosure, the solvent preferably includes water.
In the transport process, the atomized liquid droplets are transported into a film formation chamber with carrier gas. The carrier gas is not particularly limited unless it interferes with the present disclosure, and preferred examples include inert gas such as oxygen, ozone, nitrogen, and argon and reducing gas such as hydrogen gas and forming gas. Although the number of kinds of the carrier gas may be one, the number of kinds of the carrier gas may be two or more, and diluted gas (such as 10-time diluted gas, for example) with a reduced flow rate may be further used as second carrier gas. In addition, the number of carrier gas supply location may not be only one and may be two or more. The flow rate of the carrier gas is not particularly limited, is preferably 0.01 L/minute to 20 L/minute and is more preferably 1 L/minute to 10 L/minute. In the case of diluted gas, the flow rate of the diluted gas is preferably 0.001 L/minute to 5 L/minute and is more preferably 0.1 L/minute to 3 L/minute.
In the film formation process, the semiconductor film is formed on the base by causing the atomized liquid droplets to thermally react in the vicinity of the base. The thermal reaction may be performed in any manner as long at the atomized liquid droplets cause a reaction with heat, and reaction conditions and the like are also not particularly limited unless it interferes with the present disclosure. In the process, the thermal reaction is typically performed at a temperature that is equal to or greater than an evaporation temperature of the solvent, is preferably equal to or less than a temperature that is not excessively high (1000° C., for example), is more preferably equal to or less than 650° C., and is most preferably 300° C. to 650° C. Moreover, although the thermal reaction may be performed in any atmosphere out of in vacuum, in a non-oxygen atmosphere (such as an inert gas atmosphere, for example), in a reducing gas atmosphere, and in an oxygen atmosphere, the thermal reaction is preferably performed in an inert gas atmosphere or in an oxygen atmosphere. Also, although the thermal reaction may be performed under any condition out of under an atmospheric pressure, under an increased pressure, and under a reduced pressure, the thermal reaction is preferably performed under an atmospheric pressure in the embodiment of the present disclosure. Note that the film thickness is able to be set by adjusting a film formation time.
The base is not particularly limited as long as the base is able to support the semiconductor film. A material of the base is not particularly limited unless it interferes with the present disclosure, the base may be a known base, and the material may be an organic compound or may be an inorganic compound. The shape of the base may be any shape, the base is effective for any shape, examples of the shape include a plate shape such as a flat plate or a disc, a fiber shape, a rod shape, a columnar shape, a prismatic shape, a tubular shape, a spiral shape, a spherical shape, and a ring shape, and the base is preferably a substrate in the embodiment of the present disclosure. The thickness of the substrate is not particularly limited in the embodiment of the present disclosure.
The substrate is not particularly limited as long as the substrate has a plate shape and serves as a support body of the semiconductor film. Although the substrate may be an insulating substrate, may be a semiconductor substrate, or may be a metal substrate or a conductive substrate, the substrate is preferably an insulating substrate or is also preferably a substrate including a metal film on the surface thereof. Examples of the substrate include an underlayer substrate containing, as a major component, a substrate material having a corundum structure, an underlayer substrate containing, as a major component, a substrate material having a β-gallia structure, and an underlayer substrate containing, as a major component, a substrate material having a hexagonal crystal structure. Here, the “major component” means that the substrate material having the specific crystal structure is contained preferably at an atomic ratio of equal to or greater than 50%, more preferably at an atomic ratio of equal to or greater than 70%, and is further preferably at an atomic ratio of equal to or greater than 90%, and may be contained at 100% with respect to all components of the substrate material.
The substrate material is not particularly limited unless it interferes with the present disclosure unless it interferes with the present disclosure and may be a known substrate material. Preferable examples of the substrate material having the corundum structure described above include α-Al2O3 (sapphire substrate) or α-Ga2O3, and more preferable examples include an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, and an α type gallium oxide substrate (an a plane, an m plane, or an r plane). Examples of the underlayer substrate containing, as a major component, a substrate material having a β-gallia structure include a f-Ga2O3 substrate and a mixed crystal substrate containing Ga2O3 and Al2O3 in which Al2O3 is greater than 0 wt % and is equal to or less than 60 wt %. Also, examples of the underlayer substrate containing, as a major component, a substrate material having a hexagonal crystal structure include an SiC substrate, a ZnO substrate, and a GaN substrate.
In the embodiment of the present disclosure, annealing processing may be performed after the film formation process. The annealing processing temperature is not particularly limited unless it interferes with the present disclosure, is typically 300° C. to 650° C., and is preferably 350° C. to 550° C. Also, the annealing processing time is typically 1 minute to 48 hours, is preferably 10 minutes to 24 hours, and is more preferably 30 minutes to 12 hours. Note that the annealing processing may be performed in any atmosphere unless it interferes with the present disclosure. The annealing processing may be performed in a non-oxygen atmosphere or may be performed in an oxygen atmosphere. Examples of the non-oxygen atmosphere include an inert gas atmosphere (such as a nitrogen atmosphere, for example) and a reducing gas atmosphere, and the annealing processing is preferably performed in an inert gas atmosphere and is more preferably performed in a nitrogen atmosphere in the embodiment of the present disclosure.
Moreover, the semiconductor film may be provided directly on the substrate, or the semiconductor film may be provided via another layer such as a stress relief layer (such as a buffer layer or an ELO layer, for example) or a removable sacrificial layer in the embodiment of the present disclosure. Means for forming each layer is not particularly limited, may be known means, and is preferably a mist CVD method in the embodiment of the present disclosure.
In the embodiment of the present disclosure, the semiconductor film may be used as the semiconductor layer for a semiconductor device after using known means such as removing from the base or the like or may be directly used as the semiconductor layer for a semiconductor device.
The semiconductor device according to the present disclosure is effective for a variety of semiconductor elements and is effective for a power device, in particular. Also, the semiconductor elements are categorized into a lateral element (lateral device) in which an electrode is formed on a side of one surface of a semiconductor layer and a current flows in a direction perpendicular to a film thickness direction of the semiconductor layer and a vertical element (vertical device) in which electrodes are included on both front and rear surfaces of a semiconductor layer and a current flows in a film thickness direction of the semiconductor layer, the semiconductor element is able to be suitably used both for a lateral device and for a vertical device in the embodiment of the present disclosure, and the semiconductor element is preferably used for a vertical device, in particular. Examples of the semiconductor element include a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a static induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), and a PiN diode (PND). In the embodiment of the present disclosure, the semiconductor device is preferably a JBS, a PND, a MOSFET, an SIT, a JFET, or an IGBT and is more preferably a JBS, a MOSFET, a PND, or an IGBT.
Although preferred examples of the semiconductor device will be described below by using the drawings, the present disclosure is not limited to these embodiments. Note that a semiconductor device illustrated below as an example may further include other layers (such as an insulating layer, a semi-insulating layer, a conductive layer, a semiconductor layer, a relief layer, and another intermediate layer, for example) unless they interfere with the present disclosure, and the relief layer (buffer layer) and the like may be appropriately omitted. Note that in the following description, a case where a first oxide semiconductor layer is a first p type oxide semiconductor layer while a second oxide semiconductor layer is a second p type oxide semiconductor is also included in the embodiments of the present disclosure.
In the IGBT in
A constituent material of the gate insulating film (interlayer insulating film) is not particularly limited and may be a known material. Examples of the material of the gate insulating film include an SiO2 film, an SiON film, an AlON film, an AlN film, an Al2O3 film, an HfO2 film, a phosphorus-added SiO2 film (PSG film), a boron-added SiO2 film (BSG film), and a phosphorus-boron-added SiO2 film (BPSG film). The material is not limited to these and may be any material that is used for a MOSFET gate insulating film. Also, the gate insulating film may be any of amorphous, polycrystalline, and monocrystalline gate insulating films, or may be a multilayer film. Examples of a method of forming the gate insulating film include a CVD method, an atmospheric pressure CVD method, a plasma CVD method, and a mist CVD method. In the embodiment of the present disclosure, the method of forming the gate insulating film is preferably a mist CVD method or an atmospheric pressure CVD method.
The collector electrode 5c, the emitter electrode 5b, and the gate electrode 5a are not particularly limited as long as the collector electrode 5c, the emitter electrode 5b, and the gate electrode 5a have electrical conductivity and unless they interfere with the present disclosure. A constituent material of the collector electrode 5c, the emitter electrode 5b, and the gate electrode 5a (hereinafter, collectively simply referred to as “electrodes”) may be a conductive inorganic material or may be a conductive organic material. In the embodiment of the present disclosure, the material of the electrode is preferably metal. Preferred examples of the metal include at least one kind of metal selected from the Groups 4 to 10 of the periodic table. Examples of the Group 4 metal of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of the Group 5 metal of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of the Group 6 metal of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of the Group 7 metal of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of the Group 8 metal of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of the Group 9 metal of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of the Group 10 metal of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). In the embodiment of the present disclosure, the emitter electrode preferably contains at least one kind of metal selected from titanium (Ti), tantalum (Ta), and tungsten (W). Also, the electrode may contain a conductive metal oxide in the embodiment of the present disclosure. Examples of the conductive metal oxide contained in the electrode include metal oxide conductive films of tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and the like. The electrode may be configured of a single layer or may include a plurality of metal layers. A method of forming the electrode is not particularly limited. Specific examples of a method of forming the electrode include a dry method, a wet method, and a mist CVD method. Examples of the dry method include sputtering, vacuum deposition, and CVD. Examples of the wet method include screen printing and die coating.
In an example, a semiconductor diode (PiN diode) including at least layers corresponding to the second p type oxide semiconductor layer 2b, the n− type oxide semiconductor layer 1a, and the n+ type oxide semiconductor layer 1b in the IGBT in
Examples of a constituent material of the ohmic electrodes 15a and 15b include materials and the like exemplified as the constituent materials of the collector electrode, the emitter electrode, and the gate electrode. Also, a method of forming the ohmic electrodes is not particularly limited. Specific examples of the method of forming the ohmic electrodes include a dry method, a wet method, and a mist CVD method. Examples of the dry method include sputtering, vacuum deposition, and CVD. Examples of the wet method include screen printing and die coating.
In the PiN diode in
In the JBS in
Hereinafter, the present disclosure will be more specifically described using a preferred example of manufacturing the semiconductor device in
In the MOSFET in
Note that it is also possible to combine a plurality of embodiments of the present disclosure described above or to apply some of the components to another embodiment, and such configurations also belong to embodiments of the present disclosure.
In order to exhibit the functions described above, the semiconductor device of the disclosure described above can be applied to a power converter such as an inverter or a converter. More specifically, it can be applied as a thyristor, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a PND that is rectifying elements (PiN Diode), JBS (Junction Barrier Schottky Diode) or the like as a switching element.
As shown in
The inverter 504 converts the DC voltage supplied from the boost converter 502 into three-phase alternating current (AC) voltage by switching operations, and outputs to the motor 505. The motor 505 is a three-phase AC motor constituting the traveling system of an electric vehicle, and is driven by an AC voltage of the three-phase output from the inverter 504. The rotational driving force is transmitted to the wheels of the electric vehicle via a transmission mechanism (not shown).
On the other hand, actual values such as rotation speed and torque of the wheels, the amount of depression of the accelerator pedal (accelerator amount) are measured from an electric vehicle in cruising by using various sensors (not shown), The signals thus measured are input to the drive control unit 506. The output voltage value of the inverter 504 is also input to the drive control unit 506 at the same time. The drive control unit 506 has a function of a controller including an arithmetic unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory, and generates a control signal using the inputted measurement signal and outputs the control signal as a feedback signal to the inverters 504, thereby controlling the switching operation by the switching elements. The AC voltage supplied to the motor 505 from the inverter 504 is thus corrected instantaneously, and the driving control of the electric vehicle can be executed accurately. Safety and comfortable operation of the electric vehicle is thereby realized. In addition, it is also possible to control the output voltage to the inverter 504 by providing a feedback signal from the drive control unit 506 to the boost converter 502.
As indicated by a dotted line in
As shown in
The control system 500 described above is not only applicable to the control system of an electric vehicle of the semiconductor device of the disclosure, but can be applied to a control system for any applications such as to step-up and step-down the power from a DC power source, or convert the power from a DC to an AC. It is also possible to use a power source such as a solar cell as a battery.
As shown in
The inverter 604 converts the DC voltage supplied from the AC/DC converter 602 into three-phase AC voltage by switching operations and outputs to the motor 605. Configuration of the motor 605 is variable depending on the control object. It can be a wheel if the control object is a train, can be a pump and various power source if the control objects a factory equipment, can be a three-phase AC motor for driving a compressor or the like if the control object is a home appliance. The motor 605 is driven to rotate by the three-phase AC voltage output from the inverter 604, and transmits the rotational driving force to the driving object (not shown).
There are many kinds of driving objects such as personal computer, LED lighting equipment, video equipment, audio equipment and the like capable of directly supplying a DC voltage output from the AC/DC inverter 602. In that case the inverter 604 becomes unnecessary in the control system 600, and a DC voltage from the AC/DC inverter 602 is supplied to the driving object directly as shown in
On the other hand, rotation speed and torque of the driving object, measured values such as the temperature and flow rate of the peripheral environment of the driving object, for example, is measured using various sensors (not shown), these measured signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measured signals, the drive control unit 606 provides a feedback signal to the inverter 604 thereby controls switching operations by the switching element of the inverter 604. The AC voltage supplied to the motor 605 from the inverter 604 is thus corrected instantaneously, and the operation control of the driving object can be executed accurately. Stable operation of the driving object is thereby realized. In addition, when the driving object can be driven by a DC voltage, as described above, feedback control of the AC/DC controller 602 is possible in place of feedback control of the inverter 604.
As indicated by a dotted line in
In such a control system 600, similarly to the control system 500 shown in
Although the motor 605 has been exemplified in
Although the semiconductor device according to the present disclosure is able to be used in any fields such as fields of semiconductors (compound semiconductor electronic devices, for example), electronic parts/electric device parts, optical/electronic photograph-related devices, industrial members, and the like, the semiconductor device is effective for power devices, in particular.
The embodiments of the present invention are exemplified in all respects, and the scope of the present invention includes all modifications within the meaning and scope equivalent to the scope of claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-004696 | Jan 2022 | JP | national |
This application is a continuation-in-part application of International Patent Application No. PCT/JP2023/000682 (Filed on Jan. 12, 2023), which claims the benefit of priority from Japanese Patent Application No. 2022-004696 (filed on Jan. 14, 2023). The entire contents of the above applications, which the present application is based on, are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/000682 | Jan 2023 | WO |
| Child | 18771277 | US |
