Semiconductor device

Abstract

The semiconductor device includes: an A/D conversion circuit; a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; and an output terminal for testing for outputting the conversion results of the A/D conversion circuit externally. The output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a main portion of a semiconductor device of Embodiment 1.

FIG. 2 is a timing chart showing the operation of the semiconductor device of Embodiment 1 during testing.

FIG. 3 is a circuit diagram of an alteration of Embodiment 1.

FIG. 4 is a circuit diagram showing a configuration of a main portion of a semiconductor device of Embodiment 2.

FIG. 5 is a timing chart showing the operation of the semiconductor device of Embodiment 2 during testing.

FIG. 6 is a circuit diagram showing a configuration of a main portion of a semiconductor device of Embodiment 3.

Claims

1. A semiconductor device comprising: an A/D conversion circuit;a digital processing circuit for performing processing based on conversion results of the AID conversion circuit; andan output terminal for testing for outputting the conversion results of the A/D conversion circuit externally,wherein the output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.

2. The device of claim 1, further comprising an output signal switch circuit, wherein the output terminal for testing is also used as an output terminal for normal operation from which a predetermined signal is output during normal operation.

3. The device of claim 1, further comprising a buffer circuit for a digital signal, wherein the conversion results of the A/D conversion circuit are outputted to the output terminal for testing via the buffer circuit.

4. The device of claim 1, further comprising an output control circuit for controlling the output timing of the conversion results to the output terminal for testing, wherein the other conversion operation of which conversion results are to be outputted later is performed in a clock cycle that does not include timing at which an output of the output control circuit changes.

5. The device of claim 4, wherein the output control circuit has a hold circuit for holding the conversion results of the A/D conversion circuit and outputting the held conversion results, wherein the other conversion operation of which conversion results are to be outputted later is performed in a clock cycle different from a clock cycle in which the hold circuit performs hold operation and a signal at the output terminal for testing changes.

6. The device of claim 4, wherein the output control circuit has a gate circuit for allowing or blocking passing of the conversion results of the A/D conversion circuit, wherein the other conversion operation of which conversion results are to be outputted later is performed in a clock cycle different from a clock cycle in which the gate circuit allows or blocks passing of the conversion results.

7. The device of claim 4, wherein the output control circuit controls the output timing of the conversion results according to a frequency-divided clock signal obtained by frequency-dividing an operation clock signal for the AID conversion circuit or a delay signal of the operation clock signal, or a frequency-divided clock signal obtained by delaying the signal obtained by frequency-dividing the operation clock signal.

8. The device of claim 4, wherein the output control circuit controls the output timing of the conversion results according to a clock signal including part of clock pulses of an operation clock signal for the A/D conversion circuit or pulses synchronizing with the part of clock pulses.

9. The device of claim 1, wherein the A/D conversion circuit performs one unit of conversion operation every plurality of clock cycles.

10. The device of claim 9, wherein the A/D conversion circuit is a pipeline type A/D conversion circuit.

11. The device of claim 9, further comprising an output control circuit for controlling the output timing of the conversion results to the output terminal for testing, wherein the output control circuit controls the output timing of the conversion results according to a frequency-divided clock signal obtained by frequency-dividing an operation clock signal for the A/D conversion circuit to have a cycle longer than the plurality of clock cycles, or a clock signal including part of clock pulses of the operation clock signal and having a cycle longer than the plurality of clock cycles.

12. The device of claim 1, wherein the A/D conversion circuit comprises: a sample-and-hold circuit for holding an input voltage; anda comparator circuit for comparing the held voltage with a predetermined reference voltage,wherein at least either timing at which the input voltage is held in the sample-and-hold circuit or timing at which comparison operation of the comparator circuit is completed is different from the output timing of the conversion results from the output terminal for testing.

13. A semiconductor device comprising: an A/D conversion circuit;a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; andan output terminal for testing for outputting the conversion results of the A/D conversion circuit externally,wherein output timing of the conversion results from the output terminal for testing is controlled according to a timing control signal input externally.

14. The device of claim 13, further comprising a hold circuit for holding an output of the A/D conversion circuit and outputting the held output to the output terminal for testing, wherein timing of the holding of the hold circuit is controlled according to the timing control signal.

15. The device of claim 13, further comprising a gate circuit for allowing or blocking passing of the conversion results of the A/D conversion circuit, wherein timing of allowing and blocking passing of the conversion results by the gate circuit is controlled according to the timing control signal.

16. A semiconductor device comprising: an A/D conversion circuit for performing AID conversion every clock cycle of an operation clock signal;a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; andan output terminal for testing for outputting the conversion results of the A/D conversion circuit externally,wherein the device further comprises an output suppression circuit for suppressing output of the conversion results to the output terminal for testing at predetermined timing.

17. The device of claim 16, wherein conversion results of conversion operation that is performed at timing at which output of conversion results of other conversion operation is suppressed are output to the output terminal for testing.