Semiconductor device

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device provided with a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which predetermined elements and a connection wiring for electrically connecting the elements are formed on each layer

In the recent years, the miniaturization of various types of wirings such as a connection wiring for mutually connection among the gate electrode of an MOS transistor, an ohmic electrode to elements and the elements, has progressed with the miniaturization of semiconductor element. As an internal structure of the semiconductor device capable of satisfying such miniaturization, a multilayer wiring structure which is a stacked structure, is widely employed. This multilayer wiring structure has advantages in that chip size can be made smaller, a LSI can be made further multifunctional and accelerated and the degree of freedom in circuit design can be improved. On the other hand, the multilayer wiring structure has disadvantages in that it has the difference in height between a portion which a connection wiring for mutually connecting elements exists and a portion on which no such connection wiring exists and the difference increases as connection wirings increasingly become multilayered. Such an increase of the difference in height may cause a malfunction such as, for example, the disconnection of a connection wiring formed or an upper layer. Conventionally, it is well known that a dummy pattern having almost the same height as that of a connection wiring is provided on a portion on which no connection wiring exists, so as to suppress the difference in height.

FIG. 7

shows one example of a dummy pattern formed on a conventional semiconductor device having a multilayer wiring structure. A dummy pattern

73

, which is almost as high as two connection wirings

72

a

and

72

b

formed on a substrate

71

and which is made of aluminum alloy, is provided so that the outer peripheral portion of the pattern

73

is adjacent to the connection wirings

72

a

and

72

b

. With this constitution, the difference in height between a portion on which the connection wirings

72

a

and

72

b

exist and a portion on which the connection wirings

72

a

and

72

b

do not exist can be suppressed. As a result, it is possible to avoid a malfunction such as the disconnection of a connection wiring (not shown) formed on an upper layer.

Meanwhile, the dummy pattern

73

is usually formed in a solid manner on a portion on which the connection wirings

72

a

and

72

b

do not exist. The area of the pattern

73

is considerably large compared with that of the connection wirings

72

a

and

72

b

. To constitute a multilayer wiring structure, patterning by means of exposure photolithography is repeated. If the connection wirings

72

a

,

72

b

and the dummy pattern

73

have such a relationship in size, a difference in surface reflection quantity occurs between the connection wirings and the dummy pattern during exposure. It is empirically known that the gap (space) between the connection wirings and the dummy pattern tends to be narrower than that between the connection wirings according to the difference in surface reflection quantity. If the gap is narrowed, short defects tends to occur between the connection wirings and the dummy pattern. If aluminum alloy is used as a material for the connection wirings, in particular, hillock (aluminum solid-phase growth) may possibly occur by a heat treatment during process. As a result, short defects may occur more frequently between the connection wirings and the dummy pattern.

Moreover, in the semiconductor device having the above-described multilayer wiring structure, a dummy pattern is normally in a floating state in which the dummy pattern is electrically isolated. In this state, the potential of the dummy pattern is unstable and there is near that wiring delay may occur to adjacent connection wirings due to the unstable potential.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above-stated technical disadvantages and it is, therefore, an object of the present invention to provide a semiconductor device capable of suppressing a short defect between a dummy pattern and a connection wiring.

It is another object of the present invention to provide a semiconductor device capable of ensuring the good potential stability of a dummy pattern.

To accomplish these objects, in a first aspect of the present invention, there is provided a semiconductor device having a multilayer wiring structure in which a plurality of layers are formed on a substrate and in which predetermined elements and a connection wiring for electrically connecting the predetermined elements are formed on each layer, characterized in that a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring; and the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.

In a second aspect of the present invention, the dummy pattern has another linearly formed portion inside of the linearly formed portion on the outer peripheral portion.

Further, in a third aspect of the present invention, the dummy pattern is provided on both sides of an isolated connection wiring.

Moreover, in a fourth aspect of the present invention, constituent portions of the dummy pattern are connected to the substrate through conductive contacts, respectively.

Additionally, in a fifth aspect of the present invention, constituent portions of the dummy pattern are connected to a connection wiring formed on an upper layer of the layer on which the dummy pattern is formed, through conductive contacts, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a plan view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 1 of the present invention;

FIG. 2

is a plan view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 2 of the present invention;

FIG. 3

is a plan view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 3 of the present invention;

FIG. 4

is a plan view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 4 of the present invention;

FIG. 5

is a longitudinal sectional view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 5 of the present invention;

FIG. 6

is a longitudinal sectional view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 6 of the present invention; and

FIG. 7

is a plan view schematically showing part of a wiring structure inside a conventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. A semiconductor device to be described herein has a multilayer wiring structure in which a plurality of layers are provided on a substrate and predetermined elements and a connection wiring for electrically connecting the elements are formed on each layer.

Embodiment 1

FIG. 1

is a plan view showing part of a wiring structure inside a semiconductor device according to Embodiment 1 of the present invention. On a base surface

1

of a layer provided in the semiconductor device

10

, a plurality of connection wirings

2

(

2

a

,

2

b

,

2

c

and

2

d

) are formed at predetermined intervals to connect various elements (not shown) incorporated in the device. As a material for these connection wirings

2

, aluminum alloy is used as is ordinarily used with a conventional technique.

A dummy pattern

3

almost as high as the connection wirings

2

is provided in an empty region, in which the connection wirings

2

and the elements do not exist, on the base surface

1

of the layer. The dummy pattern

3

is provided so that the outer peripheral portion of tie dummy pattern

3

is adjacent to the connection wirings

2

b

and

2

c

defining the empty region. By providing so, no difference in height between a portion on which the connection wirings

2

exist and a portion on which the connection wirings

2

do not exist, occurs on the base surface

1

and it is possible to avoid the disconnection of a connection wiring (not shown) formed on the upper layer of the constitution of the base surface

1

.

In this embodiment 1, the dummy pattern

3

consists of a solid portion

3

a

formed in a solid manner and a linear portion

3

b

formed linearly around the solid portion

3

a

. The distance between the solid portion

3

a

and the linear portion

3

b

is set to be equal to or narrower than the distance between the connection wirings

2

b

,

2

c

and the linear portion

3

b.

With this structure, the distance (space) between the linear portion

3

b

and the solid portion

3

a

is narrower than that between the connection wirings

2

b

,

2

c

and the linear portion

3

b

. Due to this, in case of conducting patterning by means of exposure photolithography, it is possible to limit the possibility of the occurrence of short defects only between the linear portion

3

b

and the solid portion

3

a

, i.e., within the dummy pattern

3

. As a result, the semiconductor device

10

can enhance the margin of short defects between the dummy pattern

3

and the connection wirings

2

and improve the deterioration of yield resulting from the short defects. Further, even if aluminum alloy is used as a material for the connection wirings

2

and hillock occurs to the surfaces of the connection wirings, it is possible to sufficiently suppress short defects between the connection wirings and the dummy pattern.

In Embodiment 1, description has been given to the connection wirings

2

and the dummy pattern

3

formed on the base surface

1

of a specific layer provided in the semiconductor device

10

. This also applies to the respective layers constituting the multilayer wiring structure.

Next, other embodiments of the present intention will be described. It is noted that the same constituent elements in the following embodiments is those in Embodiment 1 are denoted by the same reference symbols, which constituent elements will not be described herein

Embodiment 2

FIG. 2

is a plan view schematically showing part of a wiring structure inside a semiconductor device according to Embodiment 2 of the present invention. As in the case of Embodiment 1 described above, a dummy pattern

23

almost as high as connection wirings

2

is provided in an empty region, in which the connection wirings

2

and elements do not exist, on the base surface

1

of a layer provided in a semiconductor device

20

. In Embodiment 2, the dummy pattern

23

consists of a linear portion

23

d

serving as an outer peripheral portion of the pattern

23

, a linear portion

23

c

inside of the linear portion

23

d

, a linear portion

23

b

inside of the portion

23

c

, and a solid portion

23

a

formed in a solid manner at the center of the pattern

23

. The distance between the linear portions and that between the linear portion

23

b

and the solid portion

23

a

are set to be equal to or narrower than the distance between the connection wirings

2

and the linear portion

23

b.

With this structure, the space between the respective linear portions and that between the linear portion

23

b

and the solid portion

23

a

are narrower than that between the connection wirings

2

b

,

2

c

and the linear portion

23

d

. Due to this, in case of conducting patterning by means of exposure photolithography, it is possible to ensure limiting the possibility of the occurrence of short defects between the linear portions and between the linear portion

23

b

and the solid portion

23

a

, i.e., within the dummy pattern

23

. As a result, it is possible to further improve the margin of short defects between the dummy pattern

23

and the connection wirings

2

in the semiconductor device

20

. Even if shrink (contraction) progresses between, for example, the connection wirings

2

, it is possible to suppress short defects from occurring between the connection wirings

2

.

Embodiment 3

FIG. 3

is a plan view schematically showing part of a wiring structure in a semiconductor device according to Embodiment 3 of the present invention On the base surface

1

of a layer provided in this semiconductor device, one connection wiring

32

is formed in an isolated manner. In Embodiment 3, dummy patterns

33

and

34

are formed on both sides of the connection wiring

32

, respectively. These dummy patterns

33

and

34

consist of linear portions

33

a

,

34

a

formed linearly and solid portions

33

b

,

34

b

formed in a solid manner, respectively. Each of the dummy patterns

33

and

34

is formed linearly on the outer peripheral portion, i.e., at side at which the dummy is adjacent to the connection wiring

32

. In each of the dummy patterns

33

and

34

, the distance between the linear portion

33

a

or

34

a

and the solid portion

33

b

or

34

b

is set to be equal to or narrower than the distance between connection wiring

32

and the linear portion

33

a

or

34

a.

With this structure, the space between the linear portion

33

a

or

34

a

and the solid portion

33

b

or

34

b

is narrower than the space between the connection wiring

32

and the linear portion

33

a

or

34

a

. Due to this, in case of conducting patterning by means of exposure photolithography, the possibility of the occurrence of short defects can be limited between the linear portions

33

a

,

34

a

and the solid portions

33

b

,

34

b

, i.e., within the dummy patterns

33

and

34

. As a result, it is possible to improve the margin of short defects between the dummy patterns

33

,

34

and the connection wiring

32

.

Embodiment 4

FIG. 4

is a plan view schematically showing part of a wiring structure in a semiconductor device according to Embodiment 4 of the present invention. As in the case of Embodiment 3 described above, one connection wiring

32

is formed in an isolated manner on the substrate

1

of a semiconductor device

40

. Dummy patterns

43

and

44

are provided at both sides of the connection wiring

32

, respectively. In Embodiment 4, the dummy patterns

43

and

44

consist of linear portions

43

a

,

44

a

formed linearly, linear portions

43

b

,

44

b

inside of the linear portions

43

a

,

44

a

, linear portions

43

c

,

44

c

inside of the linear portions

43

b

,

44

b

and linear portions (indicated by broken lines) further inside. In each of the dummy patterns

43

and

44

, the distance between the linear portions is set to be equal to or narrower than the distance between the linear portion

43

a

or

44

a

and the connection wiring

32

.

With this structure, the space between the linear portions is narrower than the space between the connection wiring

32

and the linear portion

43

a

or

44

a

. Due to this, in case of conducting patterning by means of exposure photolithography, the possibility of the occurrence of short defects can be limited between the linear portions, i.e., within the dummy patterns

43

and

44

. As a result, in the semiconductor device

40

, it is possible to improve the margin of short defects between the dummy patterns

43

and

44

and the connection wiring

32

.

Embodiment 5

FIG. 5

is a longitudinal sectional view schematically showing part of a wiring structure in a semiconductor device according to Embodiment 5 of the present invention. In

FIG. 5

, two layers L

1

and L

2

provided on the substrate

51

of a semiconductor device

50

are shown. The ranges of these layers L

1

and L

2

are defined by interlayer insulating films

53

and

55

, respectively. The interlayer films

53

and

55

seal the constituent elements (e.g., elements and connection wirings) contained in the respective lakers L

1

and L

2

. On the layer L

2

, a dummy pattern

3

having a linearly formed outer peripheral portion is provided to be adjacent to a connection wiring

2

as in the case of Embodiment 1 described above. In this case, the upper surface of the layer L

1

become the base surface

1

of the layer L

2

on which the connection wiring

2

and the dummy pattern

3

are arranged.

In Embodiment 5, a solid portion

3

a

and a linear portion

3

b

which constitute the dummy pattern

3

on the layer L

2

are connected to the substrate

51

through conductive contacts

52

, respectively. With this structure, it is possible to prevent the solid portion

3

a

and the linear portion

3

b

, which constitute the dummy pattern

3

, from being electrically isolated and turning into a floating state and to thereby keep the potential of the dummy pattern

3

stable. As a result, it is possible to avoid the occurrence of wiring delay based on the unstable potential of the dummy pattern

3

.

Embodiment 6

FIG. 6

is a longitudinal sectional view schematically showing part of a wiring structure in a semiconductor device according to Embodiment 6 of the present invention. In

FIG. 6

, three layers L

1

, L

2

and L

3

provided on the substrate

51

of a semiconductor device

60

are shown. As in the case of Embodiment 5 described above, the ranges of these layers L

1

, L

2

and L

3

are defined by interlayer insulating films

53

,

55

and

57

, respectively. The interlayer films

53

,

55

and

57

seal constituent elements (e.g., elements and connection wiring) contained in the respective layers L

1

, L

2

and L

3

. A dummy pattern

3

having an outer peripheral portion formed linearly is provided on the layer L

2

to be adjacent to the connection wiring

2

as in the case of Embodiment 1 described above.

In Embodiment 6, the solid portion

3

a

and the linear portion

3

b

which constitute the dummy pattern

3

are connected to a connection wiring

62

formed on the layer L

3

above the layer L

2

on which the dummy patters

3

is formed, through conductive contacts

61

, respectively. In addition, in this case, the connection wiring

2

on the layer L

2

is connected to the substrate

51

and to the connection wiring

62

on upper the layer L

3

through contact elements

63

and

65

, respectively.

With this structure, it is possible to prevent the solid portion

3

a

and the linear portion

3

b

, which constitute the dummy pattern

3

, from being electrically isolated and turning into a floating state, and to thereby keep the potential of the dummy pattern

3

stable. As a result, it is possible to avoid the occurrence of wiring delay based on the unstable potential of the dummy pattern

3

.

Needless to say, the present invention should not be limited to the embodiments illustrated so far and various improvements and design changes can be made within the scope of the present invention.

As is obvious from the above description, according to the present invention, a narrower space is formed in the dummy pattern than the space between the connection wiring and the dummy pattern, and therefore, in case of conducting patterning by means of exposure photolithography, the possibility of the occurrence of short defects can be limited within the dummy pattern. As a result, in the semiconductor device, the margin of short defects between the dummy pattern and the connection wiring can be improved and the deterioration of yield resulting from the short defects can be improved.

Further, according to the present invention, it is possible to prevent the respective constituent portions from being electrically isolated and turning into a floating state and to keep the potential of the dummy pattern stable. As a result, it is possible to prevent the occurrence of wiring delay based on the unstable potential of the dummy pattern.

Semiconductor device

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

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US

International Classifications

Abstract

Description

Claims

Priority Claims (1)

US Referenced Citations (1)