Patent Application
20070134861
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of transistors.
Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.
A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET). A transistor typically includes a gate dielectric disposed over a channel region, and a gate formed over the gate dielectric.
The most common materials typically used are silicon dioxide (SiO2) as a gate dielectric material and polysilicon as a gate material. These materials have been preferred materials for transistors for many years because of their superior physical and electrical properties on a silicon substrate. However, the rapid progress in the scaling or reduction in size of transistors, including a reduction in the thickness of the gate dielectric, is pushing the limit of the use of these materials, because of unacceptable leakage current.
MOSFETs having a gate dielectric comprising SiO2 and a gate material comprising polysilicon suffer from a poly-depletion effect and/or a gate-depletion effect, because the gate electric field inverts a channel within the substrate and depletes the polysilicon gate; i.e., holes or electrons are pushed away in the polysilicon gate proximate the gate dielectric. Thus, the gate capacitance is decreased; i.e., the effective electrical thickness of the gate dielectric is increased, resulting in drive current degradation. Drive current degradation is a critical performance issue, and can result in a large interconnect capacitance signal delay in an interconnect network (e.g., comprising conductive lines), for example.
The poly-depletion effect is particularly problematic for dual-poly (e.g., the gates of the PMOS (pMOSFET) device and NMOS (nMOSFET) device are implanted with different dopant species) complementary MOS (CMOS) devices in scaled CMOS technology, as shown in
There is a trend in the semiconductor industry toward the use of high dielectric constant (k) dielectric materials having a dielectric constant or k value of greater than 4.0, for example, as a potential replacement for SiO2 as gate dielectric materials. For example, hafnium-based dielectric materials are one type of high k dielectric material under consideration for use as a gate dielectric. Although a significant reduction in leakage current has been achieved by the use of high k dielectric materials as gate dielectric materials, some serious problems still remain, such as the poly depletion effect and the formation of poor quality ultra-thin uniform high-k dielectric films (e.g., the films are non-continuous when deposited), which further hamper the scaling or reduction in size of CMOS technology.
Thus, what are needed in the art are improved transistor designs and methods of manufacture thereof.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide novel methods of forming transistors and structures thereof.
In accordance with a preferred embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a workpiece, forming a gate dielectric material over the workpiece, the gate dielectric material comprising an insulator and at least one metal element, and forming a conductive material over the gate dielectric material. The conductive material comprises the at least one metal element of the gate dielectric material.
The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 12 is a graph of capacitance versus voltage of a transistor manufactured in accordance with an embodiment of the present invention that does not exhibit a poly depletion effect;
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Various approaches have been tried to alleviate the poly depletion problem, but the prior art approaches have serious drawbacks. For example, in a paper entitled, “A Polycrystalline-Si1-xGex-Gate CMOS Technology,” by T. King et al., published in IEDM, 1990, pp. 253-256, which is incorporated herein by reference, the use of polySiGe for a gate electrode is disclosed, which may be able to increase the dopant solubility and therefore the dopant concentration in the polysilicon. However, the process described is quite complicated. Furthermore, the Ge concentration control has an effect on the work function of the gate electrodes: because of this, control of the threshold voltage Vt can be problematic. Additionally, oxides of Ge are soluble in water, making gate profile control difficult.
Another approach to solve the poly depletion problem involves the use of laser thermal processing, as described in a paper entitled, “Reduction of Polysilicon Gate Depletion Effect in NMOS Devices Using Laser Thermal Processing” by Y. F. Chong, et al., in Electrochemical and Solid-State Letters 7, 2004, pp. G25-G27, which is incorporated herein by reference. Laser thermal processing may enhance the non-equilibrium concentration of the solid solution of the gate dielectric material. However, drawbacks of this approach include a high cost and many unknown factors, such as the laser annealing or temperature distribution variation is extremely sensitive to surface reflection. Other disadvantages include a deleterious effect of higher activation energy on fixed charge density, junction leakage, gate leakage, and reliability.
In yet another approach, described in a paper entitled, “Feasibility of using W/TiN as Metal Gate for Conventional 0.13 μm CMOS Technology and Beyond,” by J. C. Hu, et al., IEDM, 1997, pp. 825-828, which is also incorporated herein by reference, the use of metal as a material for gates is disclosed. However, disadvantages of this approach include the introduction of metal deposition into conventional CMOS process integration, for which there is a concern for metal thermal stability with the gate dielectric and/or polysilicon gate. Etching, adhesion, and contamination problems are obstacles to be overcome, as well. In addition, the increased complexity of the CMOS manufacturing process due to the metal gate deposition process results in a higher cost. The complexity of the interface between the metal and gate dielectric may contribute to the unstable work function problem that this approach tends to create.
The present invention will be described with respect to preferred embodiments in a specific context, namely in the fabrication of CMOS devices. The invention may also be applied, however, to the fabrication of other transistor devices where the formation of a dielectric material adjacent a conductive material is required, for example.
Embodiments of the present invention achieve technical advantages by providing novel methods of forming transistors and structures thereof. In some embodiments, the gate dielectric material is exposed to a treatment process to form a conductive material at a top portion of the gate dielectric material, shown in
The surface of the workpiece 102 may be cleaning using a pre-gate cleaning process, e.g., to remove any contaminants or native oxide from the top surface of the workpiece 102. The pre-gate cleaning process may comprise NH4OH, H2O2, and H2O; HCl, H2O2, and H2O; or HF and H2O; as examples, although the pre-gate cleaning process may alternatively comprise other chemistries.
In an optional step, the workpiece 102 is exposed to a pretreatment process 104 to form an interface region 110 near the top surface of the workpiece 102, as shown in
In another embodiment, the interface region 110 is formed during the deposition process 106 to form the gate dielectric material 108, as shown in
Next, a deposition process 106 is used to form a gate dielectric material 108 over the top surface of the workpiece 102, as shown in
The gate dielectric material 108 preferably comprises a thickness of about 20 to 40 Angstroms or less, depending on the dielectric constant of the gate dielectric material 108, for example, although alternatively, the gate dielectric material 108 may comprise other dimensions, for example. The thickness of the gate dielectric material 108 may comprise a thickness comprising dimension d1, as shown.
The gate dielectric material 108 preferably includes a metal element in one embodiment. For example, the metal element preferably comprises Hf, Zr, La, Al, Ti, Ta, Sr, Bi, Ba, Y, Pr, Pb, Sm, Eu, Nd, Sc, Mg, Co, W, Ir, Be, Ce, Gd, Dy, Ga, and/or Pd, or combinations thereof, although alternatively, the metal element may comprise other materials. The gate dielectric material 108 preferably comprises at least one metal element, for example.
In one embodiment, the deposition process 106 for the gate dielectric material 108 results in the formation of an interface region 110. In this embodiment, the optional pretreatment process 104 previously described herein to form an interface region 110 is not required. Rather, the interface region 110 forms as a result of the deposition process 106. For example, if the deposition process 106 comprises depositing Hf, the interface region 110 may comprise Si—O, Hf—O and/or Hf—Si—O bonds. The interface region 110 preferably comprises a thickness of about 20 Angstroms or less, and reduces the effective oxide thickness (EOT) (e.g., of the gate dielectric material 108) of the transistor, for example.
After the gate dielectric material 108 is formed, the surface of the gate dielectric material 108 may subjected to an optional first treatment process (not shown in the figures). The first treatment process may comprise exposing the surface of the gate dielectric material 108 to SiH4, SiCl2H2, di-silane, diluted SiF4, or other silicon-containing substances, as examples, although alternatively, other materials may also be used. The optional first treatment process prevents an increase in the thickness of the interface region 110, smoothes the surface of the gate dielectric material 108, and/or cures defects in the gate dielectric material 108 and/or the interface region 110, as examples. In one embodiment, for example, the optional first treatment process may prevent pinning of the threshold voltage, which can occur in MOSFET devices with high k materials as a gate dielectric material, as an example.
Next, in accordance with embodiments of the present invention, the top surface of the gate dielectric material 108 is treated with a second treatment process 120, as shown in
The novel second treatment process 120 may comprise a thermal nitridation process, a plasma nitridation process, a gate dielectric material reduction process, or a catalytic reaction process, as examples, although other methods of converting a portion of the gate dielectric material 108 to a conductive material 122 may also be used. Preferred second treatment processes 120 will be described next.
In one embodiment, the second treatment process 120 comprises a thermal nitridation process, for example. The workpiece 102 is preferably heated in a chamber in the presence of a nitrogen-containing gas, e.g., at a temperature of about 700 to 800 degrees C. The gate dielectric material 108 may be exposed to a nitrogen-containing gas such as NH3 for about 20 to 60 minutes, as examples. However, other temperatures, gases, and processing times may also be used. For example, if the gate dielectric material 108 comprises a metal element M, Si and O, then the thermal nitridation process results in the reaction: MSiO+NH3→MN or MSiN. Thus, the conductive material 122 comprises MN or MSiN in this embodiment, comprising a thickness of about 10 Angstroms or less, although alternatively, the conductive material 122 may comprise other conductive materials and dimensions, for example.
In another embodiment, the second treatment process 120 comprises a plasma nitridation process, for example. The workpiece 102 is preferably exposed to plasma in a chamber in the presence of a nitrogen-containing gas, e.g., at a temperature of about 200 to 300 degrees C. The gate dielectric material 108 may be exposed to a nitrogen-containing gas such as NH3 for about 20 to 300 seconds, as an example, although other temperatures, gases and processing times may be used. For example, if the gate dielectric material 108 comprises a metal element M, Si, and O, then the plasma nitridation process results in the reaction: MSiO+NH3→MN or MSiN. Thus, the conductive material 122 comprises MN or MSiN in this embodiment comprising a thickness of about 10 Angstroms or less, although alternatively, the conductive material 122 may comprise other conductive materials and dimensions, for example.
If the second treatment process 120 comprises a thermal or plasma nitridation process, the second treatment process 120 preferably comprises exposing the gate dielectric material 108 to a nitrogen-containing gas, optionally combined with an O2, CO, or CO2, as examples.
In another embodiment, the second treatment process 120 comprises a gate dielectric material 108 reduction process, for example. The gate dielectric material reduction process preferably comprises exposing the gate dielectric material 108 to a hydrogen species, e.g., at a lower temperature and then to a higher temperature, during exposure to a reduction reaction activation energy. The temperatures may vary depending on the level of the reduction reaction activation energy, for example. The temperatures may comprise about 450 to 750 degrees C., as examples, although other temperatures may be used. The exposure to the hydrogen species preferably comprises exposing the gate dielectric material 108 to a hydrogen-containing gas such as H2, as an example. Alternatively, other temperatures, hydrogen-containing gases, or deuterium-containing gases may also be used. For example, if the gate dielectric material 108 comprises a metal element M, and if the gate dielectric material 108 also comprises Si and O, then the gate dielectric material reduction process results in the reaction: MSiO+H→MSi+OH or H2O. Thus, the conductive material 122 comprises MSi in this embodiment comprising a thickness of about 10 Angstroms or less, although alternatively, the conductive material 122 may comprise other conductive materials and dimensions, for example. The hydrogen species removes oxygen away from the gate dielectric material 108 in this embodiment, for example, and forms a conductive material 122 at a top surface of, e.g., at a top portion of the gate dielectric material 108. The byproducts of the gate dielectric reduction process, OH and/or H2O, may be removed using a cleaning process or may be vaporized, for example.
In yet another embodiment, the second treatment process 120 comprises a catalytic reaction process, for example. The gate dielectric material 108 is preferably exposed to a catalyst, such as a metal organic precursor such as MO(CH2)x. Alternatively the catalyst may comprise a dielectric material, such as MO or MSiO, as examples. The gate dielectric material 108 is preferably exposed to the catalyst or the metal organic precursor at a temperature sufficient to cause a catalytic reaction, e.g., at a temperature greater than room temperature, for about 30 minutes or less, as examples. Alternatively, other catalysts, temperatures, and processing times may be used. For example, if the gate dielectric material 108 comprises a metal element M, Si, and O, then the catalytic reaction process results in the reaction: MSiO+Catalyst or Metal-organic precursor→MSi. Thus, the conductive material 122 comprises MSi in this embodiment, comprising a thickness of about 10 Angstroms or less, although alternatively, the conductive material 122 may comprise other conductive materials and dimensions, for example.
After the second treatment process 120, the conductive material 122 is disposed on the top surface of the gate dielectric material 108, as shown in
Next, a layer of semiconductor material 124 is formed on the top surface of the conductive material 122, as shown in
The manufacturing process of the semiconductor device 100 is then continued, as shown in
One or more insulating materials (not shown) may be deposited over the transistor 130, and contacts (also not shown) may be formed in the insulating materials in order to make electrical contact with the gate 122/124, source S and/or drain D. Additional metallization and insulating layers may be formed and patterned over the top surface of the insulating material and contacts. A passivation layer may be deposited over the insulating layers. Bond pads may be formed over contacts, and the semiconductor device 100 may then be singulated or separated into individual die. The bond pads may be connected to leads of an integrated circuit package (not shown) or other die, for example, in order to provide electrical contact to the transistor 130 of the semiconductor device 100.
The novel treatment process 120 of embodiments of the present invention advantageously converts a portion of the gate dielectric material 108 to a conductive material 122 disposed over the top surface of the gate dielectric material 108, reducing the thickness of the gate dielectric material 108 and creating a conductive and/or metallic surface, e.g., on the top surface of the conductive material 122, with improved adhesion and bonding properties for the layer of semiconductor material 124 that is formed over the conductive material 122. The gate electrode of the transistor 130 comprises the conductive material 122 and the layer of semiconductive material 124.
Only one transistor is shown in
In another preferred embodiment of the present invention, the conductive material 222 is formed in-situ as part of the deposition process 240 for the gate dielectric material 208, as shown in a cross-sectional view in
In this embodiment, during the deposition process of the gate dielectric material 208 shown in
The third substance 241 preferably comprises a reaction gas that is adapted to convert the precursor metal element of the at least one second substance 240 into a material layer, e.g., to form the gate dielectric material 208 on the workpiece 202. The third substance 241 may comprise O2 or O3, as examples, although alternatively, the third substance 241 may comprise other gases. The third substance 241 may be adapted to oxidize the metal element of the at least one second substance 240 and form a metal oxide of the metal element, for example, forming an insulating material that comprises the gate dielectric material 208, as shown in
Next, without removing the workpiece 202 from the chamber, the substances 240 and 241 introduced into the chamber are preferably altered to cause the formation of a conductive material 222, as shown in
In another embodiment, to form the conductive material layer 222, rather than introducing a first substance 242, a reduced amount of the third substance 241 is introduced into the chamber with the at least one second substance 240, as shown in phantom in
As an example, after the workpiece 202 is placed into a deposition chamber, a first portion of the deposition process comprises introducing the at least one second substance 240 and the third substance 241 into the deposition chamber. The first portion of the deposition process may be continued for a predetermined time period, e.g., about 10 minutes. The first portion of the deposition process may include introducing at least one second substance 240 containing at least one metal element M and a third substance 241 such as O2 to form a dielectric material layer 208 comprising MO2 that includes the metal element M (e.g., comprising a metal element as described for the embodiment shown in
The in-situ flow deposition embodiment shown in
Advantageously, a CMOS device may be manufactured comprising a PMOS transistor 330a and an NMOS transistor 330b, as shown in
Part of the workpiece 302 may be masked while another part is processed as described herein. P type materials 308a, 322a, and 324a may be formed on the PMOS device 330a, and N type materials 308b, 322b, and 324b may be formed on the NMOS device 330b in this manner, for example.
In one embodiment, a different treatment process (such as the treatment process 120 shown in
As an example, before the deposition of the gate dielectric material 308a and 308b, the NMOS device 330b portion of the workpiece 302 may be masked, and the conductive material 322a of the PMOS device 330a may be formed by depositing the gate dielectric material 308a, and converting a portion of the gate dielectric material 308a to the conductive material 322a using a treatment process (such as the treatment process 120 shown in
In another embodiment, rather than using an in-situ deposition process to form the NMOS device 330b portion, a different treatment process may be used than was used for the PMOS device 330a portion. For example, the gate dielectric material 308a and 308b may be formed in a single deposition step over the entire workpiece 302, and then two different treatment processes may be used to form the conductive material 322a and 322b for the PMOS device 330a and NMOS device 330b, respectively, by masking one portion of the workpiece 302 while the other portion of the workpiece 302 is treated.
Advantageously, treatment processes 120, in-situ deposition processes, and materials 308a, 322a, 324a, 308b, 322b, and 324b may be selected to optimally integrate the processes described herein into a CMOS device manufacturing process flow, for example.
Also, the gate dielectric of a transistor may be substantially reduced in thickness in accordance with embodiments of the present invention. For example, referring to
Experimental results of embodiments of the present invention show that functional devices may be formed based on the embodiments described herein. For example, a high k dielectric material 108 comprising HfSiO (where indices to denote stoichiometry are omitted) was converted into a conductive material 122 comprising HfSiN or HfSiON (where indices to denote stoichiometry are omitted) using a thermal nitridation process 120. The thermal nitridation process 120 was easily implemented into a conventional CMOS device process flow, and a poly depletion effect was eliminated. A uniform inversion thickness Tinv was formed for devices across a 12 inch wafer, for example.
In
Advantageously, the formation of the conductive material 122/222/322 results in a material stack for a gate electrode/gate dielectric of a transistor that results in the elimination of a poly depletion effect. The conductive material 122/222/322 may be very thin; e.g., it may comprise a few monolayers of conductive material. A conductive material 122/222/322 having a thickness of about 5 to 10 Angstroms or less is adequate to screen electrostatic interaction between poly-Si and gate dielectrics, therefore eliminating the poly depletion effect.
Converting part of high-k gate dielectric 108/208/308 (e.g., comprising a metal oxide) into a conductive material layer 122/222/322 results in the consumption of part of the high k material layer 108/208/308, and also makes the high k material layer 108/208/308 thinner and more uniform, which cannot be easily achieved by deposition techniques, therefore providing the ability to scale down device 100/200/300 sizes even further. The conductive material 122/222/322 forms a process-induced metal bond between the gate dielectric material 108/208/308 and the layer of semiconductive material 124/324. MOSFET devices comprising polysilicon gates 124/324 and high k gate dielectric materials 108/208/308 may be further scaled or reduced in size, and have improved device performance, in accordance with embodiments of the present invention, without a significant increase in manufacturing costs.
Advantageously, an additional metal deposition step is not required to form the conductive material 122/222/322 described herein. The treatment processes and in-situ deposition processes described herein are used to form a conductive material 122/222/322 that forms a metallic bond or thin conductive layer 122/222/322 between the polysilicon (e.g., the layer of semiconductor material 124/324) and the high-k dielectric material (the gate dielectric material 108/208/308).
Appropriate conditions can be used to form a metallic bond/thin metal layer 122/222/322 between polysilicon 124/324 and the high k dielectric material 108/208/308, such as M-N, M-Si, M-C, or M-Si—N bonds. For example, the conductive material 122 may comprise M-N, M-Si, M-C, or M-Si—N bonds between the layer of semiconductive material 124 and the gate dielectric material 108. One example is nitridation-induced metallic bonds on hafnium-based high k dielectric materials 108/208/308 such as HfO2 or HfSiO. Sources for the conductive material 122/222/322 may comprise a reaction between poly-silicon and the high k dielectric materials 108/208/308, such as HfSiON forming HfSiN or HfSi bonds; or nitridation itself, forming HfN bonds, as examples.
Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
