Claims
- 1. A semiconductor chip set, comprising:a first semiconductor chip having a first plurality of terminals; and a second semiconductor chip having a second plurality of terminals, wherein said first and second semiconductor chips are a mirror pair, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
- 2. A semiconductor chip, comprising:a first plurality of terminals, said semiconductor chip being one-half of a mirror pair of semiconductor chips, wherein the other half of said mirror pair is a second semiconductor chip having a second plurality of terminals, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
- 3. The chip of claim 2, wherein said first plurality of terminals comprise:at least one input-output terminal; at least one input only terminal; at least one ground terminal; and at least one power terminal.
- 4. The chip of claim 3, wherein said at least one power terminal comprises at least one power terminal for CMOS input and output pins.
- 5. The chip of claim 3, wherein said at least one power terminal comprises at least one power terminal for RDRAM core and interface logic.
- 6. The chip of claim 3, wherein said at least one power terminal comprises at least one power terminal for RDRAM analog circuitry.
- 7. The chip of claim 3, wherein said at least one power terminal comprises at least one power terminal for threshold reference voltage for RSL signals.
- 8. The chip of claim 2, wherein said first plurality of terminals are arranged whereby the two members of each of the following pairs of terminal assignments are in opposite positions relative to an imaginary axis bisecting said chip:DQ8-DQ7, DQ3-DQ4, DQ0—DQ0, RQ4-RQ3, RQ0-RQ5, CTMN-CFMN, CTM-CFM, DQ3-DQ4, DQ8-DQ7, GND—GND, VCMOS-VDD, VDD—VDD, GND—GND, VDD—VDD, GND-GNDa , GND—GND, VCMOS-VDD, GND—GND, SIO0-SIO1, DQ6-DQ5, DQ2-DQ1, RQ1-RQ2, RQ7-RQ6, VREF-VDDa, DQ1-DQ2, DQ6-DQ5, and SCK-CMD.
- 9. The chip of claim 2, wherein said first plurality of terminals are arranged in six columns and nine rows, said first plurality of terminals being arranged in said columns and rows according to the following table:DQ8GNDSIO0SIO1GNDDQ7DQ3VCMOSDQ6DQ5VDDDQ4DQ0VDDDQ2DQ1VDDDQ0RQ4GNDRQ1RQ2GNDRQ3RQ0VDDRQ7RQ6VDDRQ5CTMNGNDVREFVDDaGNDaCFMNCTMGNDDQ1DQ2GNDCFMDQ3VCMOSDQ6DQ5VDDDQ4DQ8GNDSCKCMDGNDDQ7.
- 10. The chip of claim 2, wherein said first plurality of terminals are arranged in six columns and nine rows, said first plurality of terminals being arranged in said columns and rows according to the following table:DQ7GNDSIO1SIO0GNDDQ8DQ4VDDDQ5DQ6VCMOSDQ3DQ0VDDDQ1DQ2VDDDQ0RQ3GNDRQ2RQ1GNDRQ4RQ5VDDRQ6RQ7VDDRQ0CFMNGNDaVDDaVREFGNDCTMNCFMGNDDQ2DQ1GNDCTMDQ4VDDDQ5DQ6VCMOSDQ3DQ7GNDCMDSCKGNDDQ8.
- 11. A memory module, comprising:a module board; and a semiconductor chip set coupled to said module board, said semiconductor chip set comprising: a first semiconductor chip having a first plurality of terminals; and a second semiconductor chip having a second plurality of terminals, wherein said first and second semiconductor chips are a mirror pair, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
- 12. The memory module of claim 11, wherein said first and second semiconductor chips are respectively mounted on opposite sides of said module board.
- 13. The memory module of claim 11, wherein said first and second pluralities of terminals are arranged whereby the two members of each of the following pairs of terminal assignments are in opposite relative to an imaginary axis bisecting each of said first and second semiconductor chips:DQ8-DQ7, DQ3-DQ4, DQ0—DQ0, RQ4-RQ3, RQ0-RQ5, CTMN-CFMN, CTM-CFM, DQ3-DQ4, DQ8-DQ7, GND—GND, VCMOS-VDD, VDD—VDD, GND—GND, VDD—VDD, GND-GNDa , GND—GND, VCMOS-VDD, GND—GND, SIO0-SIO1, DQ6-DQ5, DQ2-DQ1, RQ1-RQ2, RQ7-RQ6, VREF-VDDa, DQ1-DQ2, DQ6-DQ5, and SCK-CMD.
- 14. A processor system comprising:a processor; and a module board electrically coupled to said processor, said module board comprising: a semiconductor chip set coupled to said module board, said semiconductor chip set comprising: a first semiconductor chip having a first plurality of terminals; and a second semiconductor chip having a second plurality of terminals, wherein said first and second semiconductor chips are a mirror pair, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
- 15. The system of claim 14, wherein said first and second semiconductor chips are respectively mounted on opposite sides of said module board.
- 16. The system of claim 14, wherein said first and second pluralities of terminals are arranged whereby the two members of each of the following pairs of terminal assignments are in opposite positions relative to an imaginary axis bisecting each of said first and second semiconductor chips:DQ8-DQ7, DQ3-DQ4, DQ0—DQ0, RQ4-RQ3, RQ0-RQ5, CTMN-CFMN, CTM-CFM, DQ3-DQ4, DQ8-DQ7, GND—GND, VCMOS-VDD, VDD—VDD, GND—GND, VDD—VDD, GND-GNDa , GND—GND, VCMOS-VDD, GND—GND, SIO0-SIO1, DQ6-DQ5, DQ2-DQ1, RQ1-RQ2, RQ7-RQ6, VREF-VDDa, DQ1-DQ2, DQ6-DQ5, and SCK-CMD.
Parent Case Info
This application is a continuation of application Ser. No. 09/388,440, filed Sep. 2, 1999, now U.S. Pat. No. 6,307,769 the entire content of which is incorporated herein by reference.
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Continuations (1)
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Number |
Date |
Country |
Parent |
09/388440 |
Sep 1999 |
US |
Child |
09/944132 |
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US |