Patent Application
20200350263
Example embodiments disclosed herein relate generally to semiconductor devices.
Semiconductor chips are used in most electronic devices today. The chips may perform a variety of signal processing and data storage functions. Examples of chips which perform data storage functions include one-time programmable (OTP) and multi-time programmable non-volatile memory.
A number of processes are performed to ensure the quality of the chips before they are sold to customers. Some processes involve programming and testing to ensure proper operation. Programming is usually performed while the die of the chip is still part of the wafer. Testing may also be performed while the die is in this state and, for example, may include scan tests and various types of functional tests. Once the dies are programmed and tested, the wafer may be cut to form the finished products.
A chip with memory may include various pins, conductive lines, or other features that are used for testing and programming during manufacture. These features may be exploited by hackers seeking unauthorized access to data stored in the chip. One hacking technique involves locating sawbow lines created when a wafer is cut. Once the sawbow lines are located on a cut die, one or more of the aforementioned features of the die may be located and used to access the stored data.
Attempts have been made to prevent memory chips and other types of semiconductor devices from being hacked. However, these attempts have proven inadequate.
A brief summary of various example embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various example embodiments, but not to limit the scope of the invention. Detailed descriptions of example embodiments adequate to allow those of ordinary skill in the art to make and use the inventive concepts will follow in later sections.
In accordance with one or more embodiments, a chip includes a circuit, a plurality of metal layers, and a portion of a sawbow line coupled to the circuit, wherein the portion of the sawbow line corresponds to the sawbow line in a cut state, the portion of the sawbow line on a first metal layer of the plurality of metal layers, and wherein the first metal layer is at least partially aligned with and overlapped by a second metal layer of the plurality of metal layers, the second metal layer at least partially hiding the portion of the sawbow line.
The chip may include a resistor coupled to the sawbow line, wherein the resistor is to set a voltage of the sawbow line to a predetermined logical value when the sawbow line is in the cut state. The chip may include logic coupled to the resistor, wherein the logic is to output a signal to disable a mode of operation of the circuit when the sawbow line is set to the predetermined logical value by the resistor. The mode of operation is a test mode and/or memory/factory program mode of the circuit. The sawbow line may carry at least one of a power supply signal, an analog test signal, or a digital test signal to or from the circuit.
In accordance with one or more embodiments, a chip includes a circuit, a plurality of metal layers, a portion of a first sawbow line coupled to the circuit, and a portion of a second sawbow line coupled to the circuit, wherein the portion of the first sawbow line corresponds to the first sawbow line in a cut state and the portion of the second sawbow line corresponds to the second sawbow line in a cut state, the portion of the first sawbow line hidden under a first metal layer of the plurality of metal layers and the portion of the second sawbow line hidden under the first metal layer or a second metal layer of the plurality of metal layers, the first sawbow line and the second sawbow line on different ones of the plurality of metal layers.
The portion of the first sawbow line may be on the second metal layer, the portion of the second sawbow line may be on a third metal layer, and the first metal layer may hide the portions of the first and second sawbow lines. The third metal layer may be aligned with and under the second metal layer and the second metal layer may hide the portion of the second sawbow line. The first resistor may be coupled to the portion of the first sawbow line and a second resistor may be coupled to the portion of the second sawbow line, wherein the first resistor is to set a voltage of the portion of the first sawbow line to a first predetermined value and the second resistor is to set a voltage of the portion of the second sawbow line to a second predetermined value. The first predetermined value may be different from the second predetermined value. The first predetermined value may be a first logical value and the second predetermined value may be a second logical value different from the first logical value.
The chip may include first logic coupled to the first resistor and second logic coupled to the second resistor, wherein at least one of the first logic and the second logic is configured to output a signal to disable a mode of operation of the circuit when the portion of the first sawbow line is set to the first predetermined value by the first resistor or when the portion of the second sawbow line is set to the second predetermined value by the second resistor. The mode of operation may be a test mode and/or memory/factory program mode of the circuit.
In accordance with one or more embodiments, a chip includes a plurality of metal layers, a portion of a first sawbow line, and a portion of a second sawbow line, wherein the portion of the first sawbow line corresponds to the first sawbow line in a cut state and the portion of the second sawbow line corresponds to the second sawbow line in a cut state, the portion of the first sawbow line hidden under a first metal layer of the plurality of metal layers and the portion of the second sawbow line hidden under the first metal layer or a second metal layer of the plurality of metal layers, the first sawbow line and the second sawbow line on different ones of the plurality of metal layers. The portion of the first sawbow line may be on different ones of the plurality of metal layers. The portion of the first sawbow line may extend in a first direction, the portion of the second sawbow line may extend in a second direction, and the first direction may cross the second direction. The first direction may be diagonal to the second direction.
The chip may include a first resistor coupled to the portion of the first sawbow line and a second resistor coupled to the portion of the second sawbow line, wherein the first resistor may be configured to set a voltage of the portion of the first sawbow line to a first predetermined value and the second resistor is configured to set a voltage of the portion of the second sawbow line to a second predetermined value when cut. The first predetermined value may be a first logical value and the second predetermined value may be a second logical value different from the first logical value.
Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings. Although several example embodiments are illustrated and described, like reference numerals identify like parts in each of the figures, in which:
It should be understood that the figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the figures to indicate the same or similar parts.
The descriptions and drawings illustrate the principles of various example embodiments. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, “or,” as used herein, refers to a non-exclusive or (i.e., and/or), unless otherwise indicated (e.g., “or else” or “or in the alternative”). Also, the various example embodiments described herein are not necessarily mutually exclusive, as some example embodiments can be combined with one or more other example embodiments to form new example embodiments. Descriptors such as “first,” “second,” “third,” etc., are not meant to limit the order of elements discussed, are used to distinguish one element from the next, and are generally interchangeable. Values such as maximum or minimum may be predetermined and set to different values based on the application.
Example embodiments describe a method for concealing features that may be used, for example, to program and/or test a semiconductor device during manufacture. The features are on or coupled to a die to be cut from a wafer and may be detected after the wafer is cut, if not for the embodiments described herein. In one embodiment, the features may include sawbow lines. Because many hacking techniques involve locating sawbow lines as an initial step, concealing the sawbow lines (or otherwise making them very hard to find) will serve as a strong deterrent to hacking.
In one embodiment, the sawbow lines on the die are arranged to be hidden by one or more overlapping metal layers. In this or another embodiment, sawbow lines may formed on one or more different metal layers to prevent detection. In these or other embodiments, the sawbow lines may be arranged in a random manner or a predetermined pattern to provide concealment. In these or other embodiments, the die circuits used to perform a test mode and/or memory/factory program mode during manufacture may be disabled as an additional security measure against hackers. By incorporating one or more of the security features into a semiconductor die, hackers will not be able to locate the sawbow lines and thus will be unable to gain access to the circuits of the die.
In one case, more than two dies may be located between adjacent dicing lanes (e.g., in a same row) may be electrically connected to one another by one or more signal lines. The signal lines may include ones used to test the dies while during a test mode prior to the wafer being cut during manufacture, e.g., factory mode testing. When the dies include semiconductor memory, the signal lines may also include ones used to program the memory prior to cutting. The signal lines may be different from ones used to test or program the dies in another embodiments. Because the signals lines will be severed during the wafer cutting process, they may be referred to as sawbow lines. In one embodiment, the sawbow lines may be used in place of pins for the die, because connector pins may be much easier to locate for hacking purposes than severed sawbow lines (which, as described below, may be hidden by other lines and thus made to be virtually undetectable).
An example embodiment includes two sawbow lines (a first sawbow line 60 and a second sawbow line 70) that connecting dies 10 and 20. While in this case the sawbow lines only connect two dies 10 and 20, in another embodiment the sawbow lines may commonly connect more than two dies (e.g., in a same row or column) of the uncut wafer. Also, while the sawbow lines in this embodiment are used to test and/or program circuits on the dies, the sawbow lines may be used for a different purpose in another embodiment. The sawbow lines may be implemented, for example, using CMOS 0.14 μm technology.
Referring to
In one embodiment, the sawbow lines 60 and 70 may be equipped with electrostatic discharge (ESD) protection 75. The ESD protection may include, for example, at least one metal layer or conductive connection between each of the sawbow lines 60 and 70 and a reference potential 90 (e.g., ground) on each die. The wafer may also include a seal ring surrounding an area including or adjacent to the first and second semiconductor dies 10 and 20. In this case, the ESD protection 75 may allow at least one (and in some cases only one) metal layer of a plurality of metal layers, and one or more vias connecting the metal layers, to be removed from the seal ring, due to less ESD influence.
In
Also, when the sawbow lines are cut, the sawbow lines 220 and 240 will be pulled up to logical 1 by resistors 260 and 280. This causes a logical 1 to be input into NOR gates 292 and 294, which, in turn, causes these NOR gates to output logical zeros to the circuits of the first and second logic that were connected to the now-cut sawbow lines 220 and 240. The circuits of the first and second logic connected to sawbow lines 220 and 240 are designed to be disabled when logical zeros are received from the outputs of the NOR gates. Disabling may include permanently disabling the ability of the dies to enter into test mode and/or memory/factory program mode. Each of the sawbow lines in
In one embodiment, cutting of the sawbow lines may cause the resistors 250, 260, 270, and 280 to be connected. This may be accomplished, for example, using a fuse or switch coupled to each sawbow line, e.g., as long as the fuse is intact the resistor is shorted out and thus has no effect. When the fuse is broken (e.g., by cutting or application of an over-current), the short no longer exists and the resistors pull up or pull down the logical states of the sawbow lines, permanently disabling the test mode and/or memory/factory program mode of operation.
Each of the first and second dies may include one metal layer or a plurality of metal layers. In order to provide an additional measure of protection against hacking, the sawbow lines may be distributed among different layers relative to one another. This may make finding the layers more difficult to locate by a hacker. As noted above, even if a hacker is able to find the cut sawbow lines, the resistors discussed in accordance with the aforementioned embodiments will disable the circuits on the dies used to implement a test mode and/or memory/factory program mode, which makes unauthorized access to stored data not possible.
In some cases, the stored data may include one or more encryption keys. A hacker may attempt to locate the sawbow lines to access these keys, in order to access data on the dies. However, the security feature(s) built into the dies as described herein will prevent access to the keys. In the event that the sawbow lines are discovered and the keys are somehow accessed, the pull-down/pull-up resistors will disable the test and program mode circuits of the dies.
The sawbow lines may be arranged in a random order or predetermined pattern in different ones of the metal layers that are vertically stacked. For example, all of the sawbow lines may be on different metal layers. As a result, one or more metal layers that do not include a sawbow line may hide a sawbow line on an underlying metal layer. In another embodiment, two or more of the sawbow lines may be on a same layer, but other overlying metal layers may still hide them. In one embodiment, the sawbow line in one of the first die 10 and the second die 20 may be on a first one of the metal layers and the same sawbow line may be on a second one of the metal layers in the other of the first die 10 and the second die 20. This may be accomplished, for example, by connecting the first metal layer to the second metal layer using different metals connected by vias in the five-metal layer structure, e.g., a via between M1 and M2, a via between M3 and M2, etc. Such an arrangement is illustrated in
Each die may also include a first logic circuit 555 and a second logic circuit 565. The first logic circuit 555 outputs signals (e.g., signals which are part of a coding scheme for test mode and/or memory/factory program signals) to the sawbow_out line connected to an adjacent die (e.g., on the right side). The second logic circuit 565 receives signals (e.g., processed in or passed through) from the adjacent die on the right side. The power supply line may power the logic circuits to perform the test mode and/or memory/factory program mode operations, and the ground line may perform ESD protection and/or may server another function. In some embodiments, the different groups of sawbow lines may be arranged throughout different metal layers. In other embodiments, at least some of the sawbow lines may be on a same metal layer. The first and second groups of sawbow lines may include the pull-up and/or pull-down resistors (as previously discussed) as an additional security feature against hacking.
Each of the dies 610 and 620 also includes a third logic circuit (with a corresponding analog circuit) 675 to exchange signals on sawbow lines with another adjacent die on an opposing side of the die. The analog circuits in each of the dies may be replaced with digital circuits (e.g., combinatorial or sequential), or a combination of analog and digital circuits may be included in each die for transmitting and receiving analog and/or digital signals on the sawbow line during a test mode and/or memory/factory program mode.
In operation, the RNG 742 sends a random signal of N bits from die 720 to die 710 through the sawbow output lines 701. The logic of the second interface circuit 750 performs a combinatorial or sequential logic function on the random signal and sends the result (e.g., M bits) back to die 720 through sawbow input lines 702. In one embodiment, M may be equal to or different from N. The logic 741 in the first circuit 740 of die 720 compares the signal received from the sawbow input line to the random signal originally sent over sawbow output line 701. Based on this comparison, a decision is made as to whether die 720 is properly operating during a test mode and/or memory/factory program mode. The sawbow lines may be arranged on the same or different metal layers as previously described, and/or pull-up and/or pull-down resistors may be used to disable a test mode and/or memory/factory program operation of the dies after a curing process is performed.
In operation, the RNG 842 outputs a random signal including N bits to the DAC 843, which converts the random digital signal into an analog signal. The analog signal is sent from die 820 to die 810 through sawbow output line 801. The second circuit 850 in die 810 converts the received analog signal to a digital signal (e.g., N bits in length) for output to die 820 through the sawbow input line 802. The logic 841 in die 820 compares the transmitted random digital signal with the received digital signal. Based on this comparison, a decision is made as to whether die 820 is properly operating during a test mode and/or memory/factory program mode. The sawbow lines may be arranged on the same or different metal layers as previously described, and/or pull-up and/or pull-down resistors may be used to disable test mode and/or memory/factory program mode operation of the dies after a curing process is performed.
In operation, the reference signal generator 941 outputs a reference signal from the die 920 to die 910 through the sawbow output line 901. When the die 910 receives the reference signal, two operations are performed. The first operation includes inputting the reference signal through a voltage divider circuit which divides the reference signal based on the values of resistors R1, R2, and R3. The values of the resistors of the voltage divider circuit may be selected to output specific values based on desired results of test data computations. The divided voltage signal output from a node between resistors R1 and R2 is sent to die 920 over the first sawbow input line 902. The comparator 942 in die 920 compares the divided voltage to a reference voltage and outputs the result to logic 944. The divided voltage signal output from a node between resistors R2 and R3 is sent to die 920 over the second sawbow input signal 903, where it is converted into a digital signal by ADC 943.
Second operation includes converting the reference signal to a digital signal using ADC 951. The logic 944 in die 920 generates a signal indicative of whether die 920 is properly operating during a test mode and/or memory/factory program mode based on the signals output from the comparator 942, the ADC 943, and the ADC of circuit 950. The programming of the logic 944 may determine how the processing is performed to render a decision. In one embodiment, the signal received on the third sawbow line may be compared to a threshold value indicative of proper operation of the die 920. The sawbow lines may be arranged on the same or different metal layers and/or pull-up and/or pull-down resistors may be used to disable test mode and/or memory/factory program mode operation of the dies after a curing process is performed.
In one implementation, the embodiment of
Moreover, the diagonal arrangement of many of these lines may add an extra measure or protection against hacking. For example, the diagonal arrangement of the sawbow lines hides the inputs/outputs illustrated in
The sawbow lines in one or more of the embodiments described herein may be cut in preparation for delivery of the finished product to a customer. To allow retesting and to handle customer returns, the integrated circuit including any of the dies discussed herein may be set to an ERROR mode if its Sawbow line(s) is/are repaired. In this case, it may be possible to get back to an INITIAL mode of operation, but all key material shall be invalidated in this case.
In one embodiment, the sawbow lines may be physical fuses. In this case, a determination may be made as to whether the die/integrated circuit is in the factory or whether it has been distributed to a customer simply by determining whether the sawbow are intact or in a cut state. This may allow the die (or its integrated circuit) to be locked or unlocked. The die may be locked, for example, when storing key or another type of encryption material. Also, in one embodiment, when the sawbow lines are intact, the die may be blanked and returned to a new state. However, once the sawbow lines are cut, the die may no longer be blanked and returned to a new state.
The processors, logic circuits, controllers, and other signal processing or signal generating features of the embodiments disclosed herein may be implemented in logic which, for example, may include hardware, software, or both. When implemented at least partially in hardware, the processors, logic circuits, controllers, and other signal processing or signal generating features may be, for example, any one of a variety of integrated circuits including but not limited to an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-chip, a microprocessor, or another type of processing or control circuit.
When implemented at least partially in software, the processors, logic circuits, controllers, and other signal processing or signal generating features may include, for example, a memory or other storage device for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods described herein.
Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other example embodiments and its details are capable of modifications in various obvious respects. As is readily apparent to those skilled in the art, variations and modifications can be affected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in any way limit the invention, which is defined only by the claims.
