Additional lead-in metallisation on a device or substrate

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements

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H01L22/32Additional lead-in metallisation on a device or substrate

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Patents Grantslast 30 patents

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Additional lead-in metallisation on a device or substrate

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor device

Cartridge for inspection

Display device and method of fabricating the same

Display device and bonding detection method of display device

Package and method of forming the same

Semiconductor structure

Semiconductor device and method for manufacturing the same

Semiconductor device and method of forming the same

Semiconductor devices having a defect detector and data storage sys...

Circuit die with isolation test structure

Semiconductor structure including interconnection to probe pad with...

Electronic device

Method for detecting resistance of side trace of display substrate...

Test structure for use in dynamic random access memory and manufact...

Motherboard and manufacturing method for motherboard

Semiconductor device assembly with pillar array

Light-emitting diode packages

PID test structure and semiconductor test structure

Metal-free frame design for silicon bridges for semiconductor packages

Semiconductor package and method of fabricating the same

Voltage contrast metrology mark

Display substrate and display device

Semiconductor device

Wire bond damage detector including a detection bond pad over a fir...

System and method for measuring device inside through-silicon via s...

Method for transferring light-emitting diode and light-emitting bas...

Scan testable through silicon VIAs

Silicon carbide semiconductor device, semiconductor package, and me...

Semiconductor device and method of manufacturing semiconductor device

Structure of semiconductor device

Patents Applicationslast 30 patents

ENABLING MICRO-BUMP ARCHITECTURES WITHOUT THE USE OF SACRIFICIAL PA...

SEMICONDUCTOR WAFER AND OPERATING METHOD OF TEST CIRCUIT OF SEMICON...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING

Testable Flip-Chip Micro-Light Emitting Diode (LED) Devices

SEMICONDUCTOR PACKAGES

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

SEMICONDUCTOR PACKAGE

ELECTRONIC DEVICE PACKAGE WITH BOARD LEVEL RELIABILITY

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

TEST STRUCTURE FOR MOL RELIABILITY EVALUATION

SEMICONDUCTOR STRUCTURES WITH COVER LAYERS

DESIGN FOR ASYMMETRIC PADS STRUCTURE AND TEST ELEMENT GROUP MODULE

HIGH BANDWIDTH MEMORY STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF

MEMORY DEVICE INCLUDING A PLURALITY OF PADS AND METHOD OF DETECTING...

SYSTEM AND METHOD FOR MEASURING DEVICE INSIDE THROUGH-SILICON VIA S...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE

SYSTEMS AND METHODS OF TESTING MEMORY DEVICES

SEMICONDUCTOR DEVICE AND INVERTER DEVICE

METHOD OF MANUFACTURING ELECTRONIC APPARATUS

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

SYSTEMS AND METHODS FOR INTERCONNECTING DIES

Four-Terminal Resistance Testing Structure

CONTACTOR FOR MULTI DEVICE SOCKETS AND RELATED

METHODS AND SYSTEMS FOR MEASURING SEMICONDUCTOR DEVICES