Semiconductor die micro electro-mechanical switch management method

Information

  • Patent Grant
  • 8704275
  • Patent Number
    8,704,275
  • Date Filed
    Friday, December 28, 2007
    16 years ago
  • Date Issued
    Tuesday, April 22, 2014
    10 years ago
Abstract
A die micro electro-mechanical switch management system and method facilitate power conservation by selectively preventing electrical current from flowing in designated components. A present invention semiconductor die comprises a block of transistors for performing switching operations, a bus (e.g., a power bus, a signal bus, etc.) for conveying electrical current and a micro electro-mechanical switch that couples and decouples the block of transistors to and from the bus. The micro electro-mechanical switch is opened and closed depending upon operations (e.g., switching operations) being performed by the block of transistors. Electrical current is prevented from flowing to the block of transistors when the micro electro-mechanical switch is open and the block of transistors is electrically isolated. The micro electro-mechanical switch can interrupt electrical current flow in a plurality of the bus lines and/or can be included in a relay array.
Description
FIELD OF THE INVENTION

The present invention relates to the field of semiconductor die management. In particular, the present invention relates to a semiconductor die micro electro-mechanical switch management system and method.


BACKGROUND OF THE INVENTION

Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reduction in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Typically, electronic systems designed to produce these results consume power. Power consumption can have undesirable impacts and power conservation is often an important design objective. However, traditional attempts at power conservation are usually limited. For example, traditional power conservation attempts do not usually reduce power consumption associated with leakage currents.


A number of electronic systems include semiconductor dies with various components that are utilized to perform a variety of operations. For example, the basic electronic component for performing switching operations in a typical semiconductor die is a transistor. Transistors typically consume energy when switching states and the more times a transistor switches states the more energy it consumes. Modern applications typically include some functions that require a semiconductor die (e.g., processor) to have a relatively large number of transistors and can require the transistor to change states a significant number of times at a relatively fast rate. However, applications also usually include a number of functions that may only involve a relatively few transistors that switch states.


A number of the electronic systems include components that significantly drain the resources and/or reduce the life of a typical limited power source even when not performing switching operations. For example, transistors typically consume some energy due to leakage current even when they are not switching states. While the power consumed by an individual transistor due to leakage current may be relatively small, the aggregate power loss for a large number of transistors can become significant. This power consumption is usually undesirable, especially in systems with limited power supplies.


There are a number of traditional mechanisms that attempt to conserve power in a semiconductor die. For example, some traditional systems attempt to conserver power by clock gating or switching off a clock to a certain number of transistors which stops the transistors from performing switching operations. However, even though the transistor is not switching states in accordance with a clock signal, transistor still typically consumes power due to leakage current. Energy resources for a number of systems are often limited and are expended quickly (e.g., battery power sources in portable devices such as a laptop computer).


SUMMARY

The present invention enables efficient selective isolation of electrical components in a semiconductor die. A present invention semiconductor die micro electro-mechanical switch management system and method facilitates power conservation by selectively preventing current from flowing in designated components and minimizing adverse impacts associated with leakage current. In one embodiment, a semiconductor die comprises a block of transistors, a bus and a micro electro-mechanical switch. The block of transistors perform switching operations. The bus conveys electric current to the transistors. The micro electro-mechanical switch couples and decouples the block of transistors to and from the bus for conveying electric current. The micro electro-mechanical switch is opened and closed depending upon operations the block of transistors are utilized for. The micro electro-mechanical switch is opened when the block of transistors are not being utilized to perform switching operations and the micro electro-mechanical switch prevents electrical current from flowing to the block of transistors when the Micro electro-mechanical switch is open. The block of transistors are electrically isolated when the micro electro-mechanical switch is open. The micro electro-mechanical switch interrupts electrical current flow in a plurality of the bus lines when the micro electro-mechanical switch is open and the micro electro-mechanical switch permits electrical current to flow to the block of transistors when the Micro electro-mechanical switch is opened. In one exemplary implementation, the bus is a power bus and/or a signal bus.





DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention by way of example and not by way of limitation. The drawings referred to in this specification should be understood as not being drawn to scale except if specifically noted.



FIG. 1 is a block diagram of an exemplary micro electro-mechanical switch semiconductor die management system in accordance with one embodiment of the present invention.



FIG. 2 is a block diagram of an exemplary micro electro-mechanical switch semiconductor die management system implemented in a graphics processing die in accordance with one embodiment of the present invention.



FIG. 3 is a flow chart of an exemplary micro electro-mechanical switch semiconductor die management method in accordance with one embodiment of the present invention.



FIG. 4A is a block diagram of a micro electro-mechanical switch in accordance with one embodiment of the present invention.



FIG. 4B is a block diagram of another exemplary micro electro-mechanical switch in accordance with one embodiment of the present invention.



FIG. 4C is a block diagram of an exemplary micro electro-mechanical switch with multiple contacts in accordance with one embodiment of the present invention.



FIG. 5 is flow chart of an exemplary semiconductor die fabrication method in accordance with one embodiment of the present invention.





DETAILED DESCRIPTION

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.


Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means generally used by those skilled in data processing arts to effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical, magnetic, optical, or quantum signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.


It should be borne in mind, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “processing”, “computing”, “calculating”, “determining”, “displaying” or the like, refer to the action and processes of a computer system, or similar processing device (e.g., an electrical, optical, or quantum, computing device), that manipulates and transforms data represented as physical (e.g., electronic) quantities. The terms refer to actions and processes of the processing devices that manipulate or transform physical quantities within a computer system's component (e.g., registers, memories, other such information storage, transmission or display devices, etc.) into other data similarly represented as physical quantities within other components.



FIG. 1 is a block diagram of semiconductor die micro electro-mechanical switch management system 100 in accordance with one embodiment of the present invention. Semiconductor die micro electro-mechanical switch management system 100 includes power component 110, signal component 115, power bus 151, signal buses 152 and 153, transistors blocks 131 through 134 and micro electro-mechanical switches 121 through 128. Power bus 151 is coupled to power component 110 and micro electro-mechanical switches 122, 124, and 125. Signal bus 152 is coupled to signal component 115 and micro electro-mechanical switches 121, 123, and 127. Signal bus 153 is coupled to micro electro-mechanical switch 128 and transistor blocks 132 and 134.


The components of semiconductor die micro electro-mechanical switch management system 100 cooperatively operate to manage power consumption while performing various operations. Power component 110 (e.g., a voltage regulator) supplies power for components of semiconductor die micro electro-mechanical switch management system 100. Power bus 151 distributes power from power component 110. In one exemplary implementation, power bus 151 is a power rail distribution system. Micro electro-mechanical switches 122, 124 and 125 couple and decouple transistor blocks 131 through 133 to and from power bus 151. Transistor blocks 131 through 134 perform transistor switching operations. Signal component 115 (e.g., a clock regulator) supplies signals for components of semiconductor die micro electro-mechanical management system 100. Signal bus 152 distributes signals from signal component 110. Micro electro-mechanical switches 121, 123 and 127 couple and decouple transistor blocks 131, 132 and 134 to and from signal bus 152. Signal buses 153 and 154 communicate signals between transistor block 132 and 134. Micro electro-mechanical switch 128 couples and decouples signal buses 153 and 154.


In one embodiment of the present invention, semiconductor die micro electro-mechanical switch management system 100 is utilized to conserve power. Micro electro-mechanical switches 122, 124, and 125 are turned off and on (e.g., contacts are opened and closed) to prevent or permit current to flow from power bus 151 to transistor blocks 131 through 133 respectively. For example, when the transistors in transistor blocks 131 through 133 are not being utilized to perform switching operations contacts in the respective micro electro-mechanical switches 122, 124, and 125 are opened. Opening and closing the contacts in micro electro-mechanical switches 122, 124 and 125 breaks the conductive path of power bus 151 preventing current from flowing to transistor blocks 131 through 133. Opening the contacts physically “isolates” transistor blocks 131 through 133 and leakage current can not flow through the transistors included in transistor blocks 131 through 133.


In one exemplary implementation, micro electro-mechanical switches 121, 123, and 127 perform a similar “isolation” function. Micro electro-mechanical switches 121, 123, and 127 are turned off and on (e.g., contacts are opened and closed) to prevent or permit current to flow from signal bus 152 to transistor blocks 131, 132 and 134 respectively. For example, when the transistors in transistor blocks 131, 132 and 134 are not being utilized to perform switching operations contacts in the respective micro electro-mechanical switches 121, 123, and 127 are opened. Opening and closing the contacts in micro electro-mechanical switches 121, 123 and 127 breaks the conductive path of signal bus 152 preventing signals from being communicated to transistor blocks 131 through 134. Opening the contacts physically “isolates” the transistor blocks 131 through 134 and leakage current can not flow through the transistors included in transistor blocks 131 through 134. In an implementation in which the signals on signal bus 152 are clock signals, the micro electro-mechanical switches 121, 123, and 127 also prevent transistors from performing switching operations by preventing the clock signal from reaching the transistors.


A micro electro-mechanical switch can also be utilized to prevent signals from flowing between transistor blocks. Micro electro-mechanical switch 129 is turned off and on (e.g., contacts are opened and closed) to prevent or permit current flow between transistor block 132 and 134. For example, when either transistor blocks 132 or 134 are not being utilized to perform switching operations contacts in micro electro-mechanical switch 129 are opened. Opening and closing the contacts in micro electro-mechanical switch 129 breaks the conductive path of signal bus 153 and 154 preventing signals from being communicated between transistor blocks 132 through 134 via signal buses 153 and 154. Opening the contacts physically “isolates” the transistor blocks and prevents signals between the transistor blocks from acting as a leakage current source.


In one embodiment of the present invention, the micro electro-mechanical switches can also be utilized to facilitate testing operations. For example, micro electro-mechanical switches 121 through 129 can be opened or closed to facilitate isolation of particular transistor blocks. The micro electro-mechanical switches 121 through 128 can be opened or closed to assist troubleshooting efforts. The micro electro-mechanical switches 121 through 128 can also be opened or closed to create different conductive paths.


It is appreciated that the present invention can be implemented in a number of different semiconductor dies. For example, FIG. 2 is a block diagram of a semiconductor die micro electro-mechanical switch management system implemented in a graphics processing die 200 in accordance with one embodiment of the present invention. Graphics processing die 200 includes power component 211, clock generator 212, three dimensional (3D) component 220, two dimensional component (2D) 230, cache 247 and dedicated graphics pipelines 240. The components of graphics processing die 200 are selectively coupled by micro electro-mechanical switches and buses. For example, micro electro-mechanical switches 244 and 245 selectively couple dedicated graphics pipelines 240 to a first power bus 291 and a second power bus 292, both of which are coupled to power component 211. Micro electro-mechanical switch 225 selectively couples and decouples 3D component 220 to and from a second clock signal bus 294. Micro electro-mechanical switches 232 and 243 selectively 2D component 230 and dedicated graphics pipeline 240 respectively to a first clock signal bus 293.


The micro electro-mechanical switches can be configured in plurality of different configurations to achieve a variety of objectives. Micro electro-mechanical switches can be coupled in series. For example, micro electro-mechanical switches 221 and 223 sequentially selectively couple 3D component 220 to a first power bus 291 and micro electro-mechanical switches 222 and 224 sequentially selectively couple 3D component 220 to a second power bus 292. The micro electro-mechanical switches can be included in a relay array configuration. For example, relay array component 270 includes a block of micro electro-mechanical switches 271 though 273 which selectively couple cache 247 to a first clock signal bus 293 coupled to clock generator 221. A relay array component can include multiple relay banks. For example, relay array component bank 250 includes a first relay bank of micro electro-mechanical switches 251 and 252 and a second relay bank of 253 and 254 which selectively couple and decouple 2D component 230 to and from power buses 291 and 292 respectively.


The micro electro-mechanical switches can be also be utilized to selectively couple and decouple signals between operational components. For example, micro electro-mechanical switch 227 selectively couples and decouples signals between 3D component 220 and 2D component 230 and micro electro-mechanical switch 231 selectively couples and decouples signals between 2D component 230 and cache 247. The micro electro-mechanical switches utilized to selectively couple and decouple signals between operational component can also be included in a relay array configuration. For example relay array 280 includes micro electro-mechanical switches 281 and 282. The micro electro-mechanical switches 241 and 242 sequentially selectively couple and decouple cache 247 and dedicated graphics pipelines 240. In one embodiment, micro electro-mechanical switches can be also be utilized to selectively couple and decouple electrical current and signals to and from external components. For example, micro electro-mechanical switch 275 through 279 selectively couples and decouples signals to and from external components (not shown).


Including multiple micro electro-mechanical switches in a path (e.g., in the path of power bus 291, signal bus 294, etc.) provides a number of potential benefits. Multiple micro electro-mechanical switches can be included in a path to help reduce wear and tear associated with making and breaking contacts on an otherwise single micro electro-mechanical switch. Multiple micro electro-mechanical switches can be included in a path to provide redundancy in case of a micro electro-mechanical switch failure or faulty operation.


It is appreciated that present invention micro electro-mechanical switches can be utilized to control leakage current at the boundaries of a die. For example, MEM switches 275 through 278 and 229 can be utilized to control the flow of current at the boundaries of graphics processing die 200. The MEM switches can be utilized to control the flow of current between multiple die coupled on a single substrate and/or multiple die stacked in a single package. For example, a present invention MEM switch can be utilized to control current flow to and/or from a communication die (e.g., for processing associated with base band communications), a memory die (e.g., a flash memory), an accessory application die (e.g., graphics, camera, music player, etc.) included in a single package (e.g. a chip in a cell phone).


It is also appreciated that present invention micro electro-mechanical switches can be controlled by a variety of different mechanisms. For example, the micro electro-mechanical switches can be controlled by hardware, software and/or combinations of both. In one exemplary implementation, operations associated with various transistor blocks (e.g. transistor blocks 131 through 134) are monitored and if switching operations within a transistor block fall below a predetermined level (e.g., not actively changing states for a predetermined period of time) then the micro electro-mechanical switches (e.g., MEM switch 122, 124 and 125 for power and MEM switch 121, 123 and 125 for signals) coupled to the transistor block can be “opened” and prevent current from flowing to the transistor block. Activities associated with various functional blocks (e.g., three dimensional (3D) component 220, two dimensional component (2D) 230, cache 247 and dedicated graphics pipelines 240) can also be monitored and if a functional block activities fall below a predetermined level (e.g., no 3D, 2D, cache or graphics pipeline activities respectively for a predetermined period of time) then the micro electro-mechanical switches coupled to the functional component can be “opened” and prevent current from flowing to the functional blocks. When additional operational operations of the transistor blocks or activities of the functional blocks are scheduled, the micro electro-mechanical switches are “closed” to permit current to flow to the respective transistor blocks and/or functional blocks.



FIG. 3 is a flow chart of semiconductor die micro electro-mechanical switch management method 300 in accordance with one embodiment of the present invention. Semiconductor die micro electro-mechanical switch management method 300 facilitates control of electrical current flow in a semiconductor chip. For example, semiconductor die micro electro-mechanical switch management method 300 can be utilized to selectively prevent electrical current from flowing to components that are not being utilized to perform switching operations.


In step 310, electrical current is supplied to a bus located in a semiconductor die. For example, the electric current can come from a component included in the semiconductor die (e.g., a power control component, a clock control component, a block of transistors, etc.) or from an external source (e.g., external power source, external clock generator, communication network, etc.). In one exemplary implementation, the bus is a power rail included in the semiconductor die.


In step 320, a micro electro-mechanical switch in the path of the bus is closed. In one embodiment, when the micro electro-mechanical switch is closed the bus is coupled to a transistor and conveys electric current to the transistor. For example, power and/or a signal is conveyed to the transistor if the micro electro-mechanical switch is closed. In one exemplary implementation, the micro electro-mechanical switch is closed if components (e.g., transistors) coupled to the micro electro-mechanical switch are being utilized to perform operations (e.g., are switching logical states).


In step 330, a micro electro-mechanical switch in the path of the bus is opened. In one embodiment, when the micro electro-mechanical switch is opened the bus is uncoupled from a transistor and electric current is not conveyed to the transistor. For example, power and/or a signal does not flow to the transistor if the micro electro-mechanical switch is opened. In one exemplary implementation, the micro electro-mechanical switch is opened if the components (e.g., transistors) coupled to the micro electro-mechanical switch are not being utilized to perform operations (e.g., are not switching logical states).


A present invention micro electro-mechanical switch can be implemented in a variety of configurations with different mechanisms. FIG. 4A is a block diagram of micro electro-mechanical switch 410 in accordance with one embodiment of the present invention. Micro electro-mechanical switch 410 includes metal layer component 411, support component 412, relief layer 413, metal contact 414, control layer 415 and substrate 417. Metal layer component 411 is coupled to support component 412 which is coupled to substrate 417. Substrate 417 is also coupled to control layer 415 and metal contact 414. Metal layer component 411 is coupled to support component 412 at one end and is fabricated with a tension so that the other end of the metal layer component 411 curls away from metal contact 414 to form a free floating end. An electrical current can be selectively applied to control layer 415. When an electrical current is applied to control layer 415 it creates an electromagnetic field that attracts the free floating end of metal layer component 411 which bends down and makes contact with metal contact 414. When metal layer component 411 is in contact with metal contact 414 the switched is closed to form a circuit and electrical current can flow from metal layer component 411 to metal contact 414. When the electrical current is removed from control layer 415 the inherent tension in metal layer component 411 pulls the metal layer component 411 away from metal contact 414 opening the switch and breaking the current flow.



FIG. 4B is a block diagram of micro electro-mechanical switch 420 in accordance with one embodiment of the present invention. Micro electro-mechanical switch 420 includes substrate 427, metal contacts 424 and 425, cog wheels 421 and 422, and metal slider 423. Substrate 427 is coupled to metal contacts 424 and 425. Substrate 427 is also coupled to micro electro-mechanical system (MEMS) motors (not shown) that rotate cog wheels 421 and 422. Cog wheels 421 and 422 are coupled so that the MEMS motors selectively rotate and drive or push metal slider 423 left and right. When micro electro-mechanical switch 420 is closed cog wheels 421 and 422 push the metal slider 423 so that metal slider 423 slides to the right and makes contact with metal contact 425 forming a path for electrical current to flow between metal contact 424 and metal contact 425. When micro electro-mechanical switch 420 is opened cog wheels 421 and 422 push the metal slider 423 so that metal slider 423 slides to the left and breaks contact with metal contact 425 decoupling the path and preventing electrical current from flowing between metal contact 424 and metal contact 4254.



FIG. 4C is a block diagram of micro electro-mechanical switch 430 with multiple contacts in accordance with one embodiment of the present invention. Micro electro-mechanical switch 430 includes insulation barriers 441 through 448 and contacts 451 through 457. Insulation barriers 441 through 444 insulate contacts 451 through 453 from one another and form contact block 491. Similarly, Insulation barriers 445 through 448 insulate contacts 454 through 457 from one another and form contact block 492. Contact blocks 491 and 492 are shown in the “open” position and the contacts 451 through 453 are not in contact with contacts 454 through 457 respectively. In the “closed” position contact blocks 491 and 492 are pushed together until the contacts 451 through 453 are in contact with contacts 454 through 457 respectively. It is appreciated there are a variety of micro electro-mechanical system (MEMS) mechanisms for pushing contact blocks 491 and 492 together to “close” micro electro-mechanical switch 430 and pulling contact blocks 491 and 492 apart to open micro electro-mechanical switch 430. For example, electric fields can be generated to attract or repel the contact blocks. Electro-mechanical system (MEMS) motors can also be utilized to push the contact blocks 191 and 192 together or pull them apart. In one exemplary implementation, insulation barriers 441 through 448 include shields that are grounded and contacts 451 through 453 form “co-axial” contacts. In one embodiment of the present invention, contacts 451 through 457 are configured to correspond to a communication protocol and the number of contacts in each side of micro electro-mechanical switch 430 can corresponds to the number of signals in a communication protocol. For example, contacts 451 and 454 communicate a particular communication protocol signal when coupled together.



FIG. 5 is flow chart of semiconductor die micro electro-mechanical switch fabrication method 500 in accordance with one embodiment of the present invention. Semiconductor die micro electro-mechanical switch fabrication method 500 can be utilized to manufacture semiconductor dies with micro electro-mechanical switches that selectively couple and decouple components to buses. For example, the semiconductor die micro electro-mechanical switches can be implemented in a configuration to selectively prevent electrical current from flowing to components that are not being utilized to perform switching operations.


In step 510, a block of transistors are fabricated in a semiconductor die. In one exemplary implementation, components of the transistor (e.g., source, drain, gate channel, emitter, collector, base, etc.) are fabricated by selectively forming regions with different electrical properties (e.g., charge, conductor, insulator, etc.). The structures are formed through repeated application of various processing steps including, oxidation, photolithography, etching, diffusion, deposition, ion implantation and annealing.


In step 520, a bus trace is laid in the semiconductor die. The bus trace can by formed by diffusion and metalization processes and can be planarized by chemical mechanical polishing techniques. In embodiment, a bus includes a plurality of trace paths. The bus can be utilized to convey an electric current. For example, the bus can be a power bus and/or a signal bus (e.g., a clock signal).


In step 530, a micro electro-mechanical switch is fabricated in the path of the bus on the die in a position to couple and decouple the path of the bus. The micro electro-mechanical switch can be utilized to prevent or permit the flow of electric current in the path of the bus. The micro electro-mechanical switch can enable hot switching. In addition, the contacts of the micro electro-mechanical switch are electrically isolated (e.g., by a grounded shield) to provided high fidelity. For example, contacts of said micro electro-mechanical switch form a coaxial connection. The contacts of the micro electro-mechanical switch can be configured to make and break a plurality of connections (e.g., in accordance with communication protocols). In one exemplary implementation, the micro electro-mechanical switch is included in a relay array.


It is appreciated that the present invention can be implemented in a variety of embodiments. In one exemplary implementation the present invention can be utilized in processing systems utilized to provide a variety of graphics applications including video games. For example, the present invention can be utilized to distribute content for use in a game console, personal computer, personal digital assistant, cell phone or any number of platforms for implementing a video game. It is also appreciated that references to video game application implementations are exemplary and the present invention is not limited to these implementations.


Thus, the present invention enables efficient selective isolation of electrical components in a semiconductor die. A present invention micro electro-mechanical switch system and method facilitates power conservation by selectively preventing current from flowing in designated components minimizing adverse impacts associated with leakage current. The present invention facilitates elimination of semiconductor leakage at a semiconductor fabrication level for an entire device. A variety of implementations can benefit from reduced leakage impacts, including handheld battery dependant devices (e.g., cell phones, portable game players, notebook computers, etc.) and larger systems (e.g., desktops, servers, supercomputers, etc.) where megawatts of power can be saved over time by reducing wait-state leakage of thousands of idle processors components.


The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims
  • 1. A semiconductor transistor block management method comprising: supplying electric current to a bus located in a semiconductor die;closing a micro electro-mechanical switch in a path of said bus; andopening said micro electro-mechanical switch in said path of said bus, wherein said micro electro mechanical switch selectively couples and decouples a block of transistors to and from a bus, wherein said micro electro mechanical switch includes a plurality of contacts and is configured to make and break a plurality of connections simultaneously and interrupts electrical current flow in a plurality of lines in said buses when said micro electro mechanical switch is open, wherein said plurality of lines are correspondingly coupled to said plurality of contacts.
  • 2. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical switch prevents electrical current from flowing to said block of transistors when said micro electro-mechanical switch is open.
  • 3. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical switch is opened when said block of transistors are not being utilized to perform switching operations and closed when said block of transistors are being utilized to perform switching operations.
  • 4. The semiconductor transistor block management method of claim 1 wherein said block of transistors are electrically isolated when said micro electro-mechanical system micro electro-mechanical switch is open.
  • 5. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical system switch permits electrical current to flow to said block of transistors when said micro electro-mechanical system relay switch is closed.
  • 6. The semiconductor transistor block management method of claim 1 wherein said opening and said closing of said electro-mechanical switch is interlinked to other electro-mechanical switches to reduce wear and tear associated with said opening and said closing.
  • 7. The semiconductor transistor block management method of claim 1 wherein said micro electro-mechanical switch is included in a micro electro-mechanical relay block.
  • 8. The semiconductor transistor block management method of claim 1 wherein said bus is a power bus and said micro electro-mechanical switch selectively turns power on and off to said block of transistors.
  • 9. The semiconductor transistor block management method of claim 1 wherein said bus is a signal bus and micro electro-mechanical switch selectively permits communication of said signal to said block of transistors.
  • 10. A semiconductor transistor block management method comprising: supplying electric current to a bus located in a semiconductor die;closing a micro electro-mechanical switch in a path of said bus, wherein said micro electro-mechanical switch includes a plurality of contacts and said closing includes closing a plurality of connections simultaneously and permits electrical current flow in a plurality of lines in said bus when said micro electro-mechanical switch is closed;opening said micro electro-mechanical switch in said path of said bus; wherein said opening includes opening a plurality of connections simultaneously and interrupts electrical current flow in a plurality of lines in said bus when said micro electro-mechanical switch is open;wherein a plurality of contacts in said micro-electromechanical switch correspond to a plurality of signals and are correspondingly coupled to said plurality of lines.
  • 11. The semiconductor transistor block management method of claim 10 wherein said bus conveys electric current to a transistor if said micro electro-mechanical switch is closed and prevents the flow of current to said transistor if said micro electro-mechanical switch is opened.
  • 12. The semiconductor transistor block management method of claim 10 further comprising: conveying power to a transistor if said micro electro-mechanical switch is closed; andpreventing power consumption by said transistor if said micro electro-mechanical switch is opened.
  • 13. The semiconductor transistor block management method of claim 10 further comprising: conveying a signal to a transistor if said micro electro-mechanical switch is closed; andblocking said transistor from receiving a signal if said micro electro-mechanical switch is opened.
  • 14. The semiconductor transistor block management method of claim 10 further comprising: receiving an indication of the operations of said block of transistors; andconfiguring a state of said micro electro-mechanical switch in accordance with said indication.
  • 15. The semiconductor transistor block management method of claim 10 further comprising: opening said micro electro-mechanical switch if said components coupled to said bus are not being utilized to perform operations; andclosing said micro electro-mechanical switch if components coupled to said bus are being utilized to perform operations.
  • 16. The semiconductor transistor block management method of claim 10 wherein a plurality of micro electro-mechanical systems switches are included is said path of said bus.
  • 17. A semiconductor transistor block management method comprising: fabricating a block of transistors in a semiconductor die;laying a bus in said semiconductor die;fabricating a micro electro-mechanical switch in the path of said bus on said die in a position to couple and decouple said path of said bus; wherein said micro electro mechanical switch includes a plurality of contacts and is configured to make and break a plurality of connections simultaneously and interrupts electrical current flow in a plurality of lines in said buses when said micro electro mechanical switch is open, wherein said plurality of lines are correspondingly coupled to said plurality of contacts.
  • 18. The semiconductor transistor block management method of claim 17 further comprising coupling said micro electro-mechanical switch to a control component for controlling operations of said micro electro-mechanical switch.
  • 19. The semiconductor transistor block management method of claim 17 wherein said micro electro-mechanical switch enables hot switching.
  • 20. The semiconductor transistor block management method of claim 17 wherein contacts of said micro electro-mechanical switch are electrically isolated to provided high fidelity and wherein said contacts are electrically isolated by a grounded shield to form a coaxial connection and said contacts of said micro electro-mechanical switch can be configured to make and break a plurality of connections.
RELATED APPLICATIONS

This application is related to the following Applications: U.S. patent application Ser. No. 10/740,721, entitled “AN INTEGRATED CIRCUIT CONFIGURATION SYSTEM AND METHOD”, filed on Dec. 18, 2003; U.S. patent application Ser. No. 10/740,722, entitled “A SYSTEM AND METHOD FOR CONFIGURING SEMICONDUCTOR FUNCTIONAL CIRCUITS”, filed on Dec. 18, 2003; U.S. patent application Ser. No. 10/740,723, entitled “A SYSTEM AND METHOD FOR INCREASING DIE YIELD” filed on Dec. 18, 2003; U.S. patent application Ser. No. 10/740,779, entitled “A SYSTEM AND METHOD FOR REMOTELY CONFIGURING SEMICONDUCTOR FUNCTIONAL CIRCUITS”, filed on Dec. 18, 2003; U.S. patent application Ser. No. 10/876,340, entitled “SYSTEM AND METHOD FOR TESTING AND CONFIGURING SEMICONDUCTOR FUNCTIONAL CIRCUITS”, filed on Jun. 23, 2004; U.S. patent application Ser. No. 10/942,169, entitled “MICRO ELECTRO MECHANICAL SWITCH SYSTEM AND METHOD FOR TESTING AND CONFIGURING SEMICONDUCTOR FUNCTIONAL CIRCUITS”, filed on Sep. 15, 2004; U.S. patent application Ser. No. 11/454,313, entitled “FUNCTIONAL COMPONENT COORDINATED RECONFIGURATION SYSTEM AND METHOD”, filed on Jun. 16, 2006; and U.S. patent application Ser. No. 11/472,865, entitled “FUNCTIONAL COMPONENT COMPENSATION RECONFIGURATION SYSTEM AND METHOD”, filed on Jun. 21, 2006. This application claims the benefit and priority of and is a Divisional of U.S. patent application Ser. No. 10/942,209, entitled “A Semiconductor Die Micro Electro-mechanical Switch Management System and Method”, filed on Sep. 15, 2004, which is incorporated herein by this reference.

US Referenced Citations (380)
Number Name Date Kind
3940740 Coontz Feb 1976 A
4208810 Rohner et al. Jun 1980 A
4412281 Works Oct 1983 A
4449730 Oberleitner et al. May 1984 A
4541075 Dill et al. Sep 1985 A
4773044 Sfarti et al. Sep 1988 A
4885703 Deering Dec 1989 A
4918626 Watkins et al. Apr 1990 A
4949280 Littlefield Aug 1990 A
4951220 Ramacher et al. Aug 1990 A
4985988 Littlebury Jan 1991 A
5036473 Butts et al. Jul 1991 A
5077660 Haines et al. Dec 1991 A
5081594 Horsley Jan 1992 A
5107455 Haines et al. Apr 1992 A
5125011 Fung Jun 1992 A
5276893 Savaria Jan 1994 A
5287438 Kelleher Feb 1994 A
5313287 Barton May 1994 A
5379405 Ostrowski Jan 1995 A
5392437 Matter et al. Feb 1995 A
5400777 Olsson et al. Mar 1995 A
5408606 Eckart Apr 1995 A
5432898 Curb et al. Jul 1995 A
5446836 Lentz et al. Aug 1995 A
5448496 Butts et al. Sep 1995 A
5452104 Lee Sep 1995 A
5452412 Johnson, Jr. et al. Sep 1995 A
5455536 Kono et al. Oct 1995 A
5483258 Cornett et al. Jan 1996 A
5498975 Cliff et al. Mar 1996 A
5513144 O'Toole Apr 1996 A
5513354 Dwork et al. Apr 1996 A
5517666 Ohtani et al. May 1996 A
5530457 Helgeson Jun 1996 A
5543935 Harrington Aug 1996 A
5570463 Dao Oct 1996 A
5574847 Eckart et al. Nov 1996 A
5578976 Yao Nov 1996 A
5594854 Baldwin et al. Jan 1997 A
5623692 Priem et al. Apr 1997 A
5630171 Chejlava, Jr. et al. May 1997 A
5633297 Valko et al. May 1997 A
5634107 Yumoto et al. May 1997 A
5638946 Zavracky Jun 1997 A
5664162 Dye Sep 1997 A
5671376 Bucher et al. Sep 1997 A
5694143 Fielder et al. Dec 1997 A
5705938 Kean Jan 1998 A
5766979 Budnaitis Jun 1998 A
5768178 McLaury Jun 1998 A
5778348 Manduley et al. Jul 1998 A
5805833 Verdun Sep 1998 A
5809230 Pereira Sep 1998 A
5815162 Levine Sep 1998 A
5821949 Deering Oct 1998 A
5854631 Akeley et al. Dec 1998 A
5854637 Sturges Dec 1998 A
5872902 Kuchkuda et al. Feb 1999 A
5884053 Clouser et al. Mar 1999 A
5896391 Solheim et al. Apr 1999 A
5909595 Rosenthal et al. Jun 1999 A
5913218 Carney et al. Jun 1999 A
5937173 Olarig et al. Aug 1999 A
5956252 Lau et al. Sep 1999 A
5956505 Manduley Sep 1999 A
5968175 Morishita et al. Oct 1999 A
5977987 Duluk, Jr. Nov 1999 A
5996996 Brunelle Dec 1999 A
5999990 Sharrit et al. Dec 1999 A
6003100 Lee Dec 1999 A
6028608 Jenkins Feb 2000 A
6034699 Wong et al. Mar 2000 A
6038348 Carley Mar 2000 A
6049870 Greaves Apr 2000 A
6065131 Andrews et al. May 2000 A
6067262 Irrinki et al. May 2000 A
6067633 Robbins et al. May 2000 A
6069540 Berenz et al. May 2000 A
6072500 Foran et al. Jun 2000 A
6072686 Yarbrough Jun 2000 A
6085269 Chan et al. Jul 2000 A
6094116 Tai et al. Jul 2000 A
6098118 Ellenby et al. Aug 2000 A
6104407 Aleksic et al. Aug 2000 A
6104417 Nielsen et al. Aug 2000 A
6115049 Winner et al. Sep 2000 A
6118394 Onaya Sep 2000 A
6128000 Jouppi et al. Oct 2000 A
6129070 Jingu et al. Oct 2000 A
6137918 Harrington et al. Oct 2000 A
6160557 Narayanaswami Dec 2000 A
6160559 Omtzigt Dec 2000 A
6188394 Morein et al. Feb 2001 B1
6201545 Wong et al. Mar 2001 B1
6204859 Jouppi et al. Mar 2001 B1
6219070 Baker et al. Apr 2001 B1
6219628 Kodosky et al. Apr 2001 B1
6249288 Campbell Jun 2001 B1
6249853 Porterfield Jun 2001 B1
6255849 Mohan Jul 2001 B1
6256758 Abramovici et al. Jul 2001 B1
6259460 Gossett et al. Jul 2001 B1
6307169 Sun et al. Oct 2001 B1
6317804 Levy et al. Nov 2001 B1
6323699 Quiet Nov 2001 B1
6323874 Gossett Nov 2001 B1
6348811 Haycock et al. Feb 2002 B1
6359623 Larson Mar 2002 B1
6362819 Dalal et al. Mar 2002 B1
6363285 Wey Mar 2002 B1
6363295 Akram et al. Mar 2002 B1
6366289 Johns Apr 2002 B1
6370603 Silverman et al. Apr 2002 B1
6377898 Steffan et al. Apr 2002 B1
6388590 Ng May 2002 B1
6389585 Masleid et al. May 2002 B1
6392431 Jones May 2002 B1
6429288 Esswein et al. Aug 2002 B1
6429747 Franck et al. Aug 2002 B2
6429877 Stroyan Aug 2002 B1
6433657 Chen Aug 2002 B1
6437780 Baltaretu et al. Aug 2002 B1
6452595 Montrym et al. Sep 2002 B1
6469707 Voorhies Oct 2002 B1
6480205 Greene et al. Nov 2002 B1
6486425 Seki Nov 2002 B2
6501564 Schramm et al. Dec 2002 B1
6504542 Voorhies et al. Jan 2003 B1
6504841 Larson et al. Jan 2003 B1
6522329 Ihara et al. Feb 2003 B1
6525737 Duluk, Jr. et al. Feb 2003 B1
6529207 Landau et al. Mar 2003 B1
6530045 Cooper et al. Mar 2003 B1
6530049 Abramovici et al. Mar 2003 B1
6535986 Rosno et al. Mar 2003 B1
6550030 Abramovici et al. Apr 2003 B1
6598194 Madge et al. Jul 2003 B1
6606093 Gossett et al. Aug 2003 B1
6611272 Hussain et al. Aug 2003 B1
6614444 Duluk, Jr. et al. Sep 2003 B1
6614448 Garlick et al. Sep 2003 B1
6624823 Deering Sep 2003 B2
6629181 Alappat et al. Sep 2003 B1
6633197 Sutardja Oct 2003 B1
6633297 McCormack et al. Oct 2003 B2
6636212 Zhu Oct 2003 B1
6646639 Greene et al. Nov 2003 B1
6662133 Engel et al. Dec 2003 B2
6671000 Cloutier Dec 2003 B1
6693637 Koneru et al. Feb 2004 B2
6693639 Duluk, Jr. et al. Feb 2004 B2
6697063 Zhu Feb 2004 B1
6700581 Baldwin et al. Mar 2004 B2
6701466 Fiedler Mar 2004 B1
6717474 Chen et al. Apr 2004 B2
6717576 Duluk, Jr. et al. Apr 2004 B1
6717578 Deering Apr 2004 B1
6718496 Fukuhisa et al. Apr 2004 B1
6734770 Aigner et al. May 2004 B2
6734861 Van Dyke et al. May 2004 B1
6738856 Milley et al. May 2004 B1
6741247 Fenney May 2004 B1
6741258 Peck, Jr. et al. May 2004 B1
6742000 Fantasia et al. May 2004 B1
6747057 Ruzafa et al. Jun 2004 B2
6747483 To et al. Jun 2004 B2
6765575 Voorhies et al. Jul 2004 B1
6778177 Furtner Aug 2004 B1
6782587 Reilly Aug 2004 B2
6785841 Akrout et al. Aug 2004 B2
6788101 Rahman Sep 2004 B1
6788301 Thrasher Sep 2004 B2
6794101 Liu et al. Sep 2004 B2
6798410 Redshaw et al. Sep 2004 B1
6803782 Koob et al. Oct 2004 B2
6803916 Ramani et al. Oct 2004 B2
6806788 Marumoto Oct 2004 B1
6819332 Baldwin Nov 2004 B2
6823283 Steger et al. Nov 2004 B2
6825847 Molnar et al. Nov 2004 B1
6833835 van Vugt Dec 2004 B1
6849924 Allison et al. Feb 2005 B2
6850133 Ma Feb 2005 B2
6861865 Carlson Mar 2005 B1
6862027 Andrews et al. Mar 2005 B2
6879207 Nickolls Apr 2005 B1
6906716 Moreton et al. Jun 2005 B2
6938176 Alben et al. Aug 2005 B1
6940514 Wasserman et al. Sep 2005 B1
6947057 Nelson et al. Sep 2005 B2
6956579 Diard et al. Oct 2005 B1
6961057 Van Dyke et al. Nov 2005 B1
6961065 Sasaki Nov 2005 B2
6966020 Abramovici et al. Nov 2005 B1
6973608 Abramovici et al. Dec 2005 B1
6978317 Anantha et al. Dec 2005 B2
6982718 Kilgard et al. Jan 2006 B2
7002591 Leather et al. Feb 2006 B1
7009607 Lindholm et al. Mar 2006 B2
7009615 Kilgard et al. Mar 2006 B1
7020598 Jacobson Mar 2006 B1
7023437 Voorhies et al. Apr 2006 B1
7043622 Henry et al. May 2006 B2
7058738 Stufflebeam, Jr. Jun 2006 B2
7061495 Leather Jun 2006 B1
7064771 Jouppi et al. Jun 2006 B1
7069369 Chou et al. Jun 2006 B2
7069458 Sardi et al. Jun 2006 B1
7069558 Stone et al. Jun 2006 B1
7075542 Leather Jul 2006 B1
7075797 Leonard et al. Jul 2006 B1
7081902 Crow et al. Jul 2006 B1
7085824 Forth et al. Aug 2006 B2
7119809 McCabe Oct 2006 B1
7124318 Luick Oct 2006 B2
7126600 Fowler et al. Oct 2006 B1
7136953 Bisson et al. Nov 2006 B1
7154066 Talwar et al. Dec 2006 B2
7158148 Toji et al. Jan 2007 B2
7170315 Bakker et al. Jan 2007 B2
7170515 Zhu Jan 2007 B1
7174407 Hou et al. Feb 2007 B2
7174411 Ngai Feb 2007 B1
7184040 Tzvetkov Feb 2007 B1
7185135 Briggs et al. Feb 2007 B1
7185225 Sutardja et al. Feb 2007 B2
7187383 Kent Mar 2007 B2
7224364 Yue et al. May 2007 B1
7246274 Kizer et al. Jul 2007 B2
7260007 Jain et al. Aug 2007 B2
RE39898 Nally et al. Oct 2007 E
7293127 Caruk Nov 2007 B2
7305571 Cranford et al. Dec 2007 B2
7307628 Goodman et al. Dec 2007 B1
7307638 Leather et al. Dec 2007 B2
7324458 Schoenborn et al. Jan 2008 B2
7340541 Castro et al. Mar 2008 B2
7362325 Anderson Apr 2008 B2
7373547 Sutardja et al. May 2008 B2
7382368 Molnar et al. Jun 2008 B1
7398336 Feng et al. Jul 2008 B2
7414636 Kokojima et al. Aug 2008 B2
7415551 Pescatore Aug 2008 B2
7424564 Mehta et al. Sep 2008 B2
7437021 Satoh Oct 2008 B2
7453466 Hux et al. Nov 2008 B2
7480808 Caruk et al. Jan 2009 B2
7483029 Crow et al. Jan 2009 B2
7525986 Lee et al. Apr 2009 B2
7548996 Baker et al. Jun 2009 B2
7551174 Iourcha et al. Jun 2009 B2
7594061 Shen et al. Sep 2009 B2
7633506 Leather et al. Dec 2009 B1
7634637 Lindholm et al. Dec 2009 B1
7663633 Diamond et al. Feb 2010 B1
7782325 Gonzalez et al. Aug 2010 B2
7791617 Crow et al. Sep 2010 B2
7793029 Parson et al. Sep 2010 B1
7965902 Zelinka et al. Jun 2011 B1
8063903 Vignon et al. Nov 2011 B2
8132015 Wyatt Mar 2012 B1
8144166 Lyapunov et al. Mar 2012 B2
8237738 Crow Aug 2012 B1
8412872 Wagner et al. Apr 2013 B1
8417838 Tamasi et al. Apr 2013 B2
8482567 Moreton et al. Jul 2013 B1
8532098 Reed et al. Sep 2013 B2
20010005209 Lindholm et al. Jun 2001 A1
20020005729 Leedy Jan 2002 A1
20020026623 Morooka Feb 2002 A1
20020031025 Shimano et al. Mar 2002 A1
20020050979 Oberoi et al. May 2002 A1
20020059392 Ellis, III May 2002 A1
20020087833 Burns et al. Jul 2002 A1
20020091979 Cooke et al. Jul 2002 A1
20020097241 McCormack et al. Jul 2002 A1
20020120723 Forth et al. Aug 2002 A1
20020130863 Baldwin Sep 2002 A1
20020138750 Gibbs et al. Sep 2002 A1
20020140655 Liang et al. Oct 2002 A1
20020143653 DiLena et al. Oct 2002 A1
20020158869 Ohba et al. Oct 2002 A1
20020158885 Brokenshire et al. Oct 2002 A1
20020196251 Duluk, Jr. et al. Dec 2002 A1
20020199110 Kean Dec 2002 A1
20030020173 Huff et al. Jan 2003 A1
20030023771 Erickson et al. Jan 2003 A1
20030046472 Morrow Mar 2003 A1
20030051091 Leung et al. Mar 2003 A1
20030058244 Ramani et al. Mar 2003 A1
20030061409 RuDusky Mar 2003 A1
20030067468 Duluk, Jr. et al. Apr 2003 A1
20030076325 Thrasher Apr 2003 A1
20030093506 Oliver et al. May 2003 A1
20030101288 Tague et al. May 2003 A1
20030115500 Akrout et al. Jun 2003 A1
20030122815 Deering Jul 2003 A1
20030160795 Alcorn et al. Aug 2003 A1
20030163589 Bunce et al. Aug 2003 A1
20030164830 Kent Sep 2003 A1
20030179631 Koob et al. Sep 2003 A1
20030194116 Wong et al. Oct 2003 A1
20030201994 Taylor et al. Oct 2003 A1
20040012082 Dewey et al. Jan 2004 A1
20040012597 Zatz et al. Jan 2004 A1
20040046764 Lefebvre et al. Mar 2004 A1
20040064628 Chiu Apr 2004 A1
20040085313 Moreton et al. May 2004 A1
20040102187 Moller et al. May 2004 A1
20040130552 Duluk, Jr. et al. Jul 2004 A1
20040183148 Blasko, III Sep 2004 A1
20040183801 Deering Sep 2004 A1
20040188781 Bar Sep 2004 A1
20040196285 Rice et al. Oct 2004 A1
20040196290 Satoh Oct 2004 A1
20040207642 Crisu et al. Oct 2004 A1
20040225787 Ma et al. Nov 2004 A1
20040227599 Shen et al. Nov 2004 A1
20040246251 Fenney et al. Dec 2004 A1
20050030314 Dawson Feb 2005 A1
20050041031 Diard Feb 2005 A1
20050041037 Dawson Feb 2005 A1
20050044284 Pescatore Feb 2005 A1
20050045722 Park Mar 2005 A1
20050060601 Gomm Mar 2005 A1
20050066148 Luick Mar 2005 A1
20050088445 Gonzalez et al. Apr 2005 A1
20050122338 Hong et al. Jun 2005 A1
20050125629 Kissell Jun 2005 A1
20050134588 Aila et al. Jun 2005 A1
20050134603 Iourcha et al. Jun 2005 A1
20050172135 Wiersma Aug 2005 A1
20050173233 Kaelberer Aug 2005 A1
20050174353 Alcorn et al. Aug 2005 A1
20050179698 Vijayakumar et al. Aug 2005 A1
20050182881 Chou et al. Aug 2005 A1
20050210472 Accapadi et al. Sep 2005 A1
20050237083 Bakker et al. Oct 2005 A1
20050246460 Stufflebeam, Jr. Nov 2005 A1
20050251761 Diamond et al. Nov 2005 A1
20050259100 Teruyama Nov 2005 A1
20050261863 Van Dyke et al. Nov 2005 A1
20050275663 Kokojima et al. Dec 2005 A1
20050278666 Diamond Dec 2005 A1
20050285863 Diamond Dec 2005 A1
20060033745 Koselj et al. Feb 2006 A1
20060044317 Bourd et al. Mar 2006 A1
20060053188 Mantor et al. Mar 2006 A1
20060053189 Mantor Mar 2006 A1
20060055641 Robertus et al. Mar 2006 A1
20060106911 Chapple et al. May 2006 A1
20060123177 Chan et al. Jun 2006 A1
20060132495 Anderson Jun 2006 A1
20060170690 Leather Aug 2006 A1
20060190663 Lu Aug 2006 A1
20060203005 Hunter Sep 2006 A1
20060221086 Diard Oct 2006 A1
20060245001 Lee et al. Nov 2006 A1
20060252285 Shen Nov 2006 A1
20060267981 Naoi Nov 2006 A1
20060267987 Litchmanov Nov 2006 A1
20060282604 Temkine et al. Dec 2006 A1
20070038794 Purcell et al. Feb 2007 A1
20070050647 Conroy et al. Mar 2007 A1
20070067535 Liu Mar 2007 A1
20070088877 Chen et al. Apr 2007 A1
20070115271 Seo et al. May 2007 A1
20070115290 Polzin et al. May 2007 A1
20070115291 Chen et al. May 2007 A1
20070139440 Crow et al. Jun 2007 A1
20070268298 Alben et al. Nov 2007 A1
20070273689 Tsao Nov 2007 A1
20070296725 Steiner et al. Dec 2007 A1
20080024497 Crow et al. Jan 2008 A1
20080024522 Crow et al. Jan 2008 A1
20080100618 Woo et al. May 2008 A1
20080198163 Nakahashi et al. Aug 2008 A1
20080273218 Kitora et al. Nov 2008 A1
20090044003 Berthiaume et al. Feb 2009 A1
Foreign Referenced Citations (16)
Number Date Country
101093578 Dec 2007 CN
61020348 Jan 1986 JP
H04266768 Sep 1992 JP
06180758 Jun 1994 JP
07-141526 Jun 1995 JP
10134198 May 1998 JP
11195132 Jul 1999 JP
11328133 Nov 1999 JP
2001-005989 Jan 2001 JP
2002076120 Mar 2002 JP
2005182547 Jul 2005 JP
1235341 Jul 2005 TW
0931127712 Jul 2005 TW
0013145 Mar 2000 WO
02054224 Jul 2002 WO
2005029329 Mar 2005 WO
Non-Patent Literature Citations (26)
Entry
Eckert, et al; Functional Component Coordinated Reconfiguration System and Method; U.S. Appl. No. 11/454,313, filed Jun. 16, 2006.
Diamond, et al; A System and Method for Remotely Configuring Semiconductor Functional Circuits; U.S. Appl. No. 10/740,779, filed Dec. 18, 2003.
Van Dyke, et al; A System and Method for Increasing Die Yield; U.S. Appl. No. 10/740,723, filed Dec. 18, 2003.
Diamond, et al; A System and Method for Configuring Semiconductor Functional Circuits; U.S. Appl. No. 10/740,722, filed Dec. 18, 2003.
Van Dyke, et al; An Integrated Circuit Configuration System and Method; U.S. Appl. No. 10/740,721, filed Dec. 18, 2003.
Diamond; Micro Electro Mechanical Switch System and Method for Testing and Configuring Semiconductor Functional Circuits; U.S. Appl. No. 10/942,169, filed Sep. 15, 2004.
Scotzniovsky, et al; Functional Component Compensation Reconfiguration System and Method; U.S. Appl. No. 11/472,865, filed Jun. 21, 2006.
Diamond; A System and Method for Configuring Semiconductor Functional Circuits; U.S. Appl. No. 10/876,340, filed Jun. 23, 2004.
Welsh, D., “Building Self-Reconfiguring Distributed Systems Using Compensating Reconfiguratuion”, Proceedings Fourth International Conference on Configurable Distributed Systems, May 4-6, 1998; pp. 18-25.
European Patent Office E-Space Family List for: WO 2005/29329 (PCT/US 2004/030127).
International Search Report. PCT/US2004/030127. Mail Date Jun. 30, 2005.
PCT International Preliminary Report on Patentability. PCT/US2004/030127. International Filing Date Sep. 13, 2004. Applicant: Nvidia Corporation. Date of Issuance of this Report: Mar. 16, 2006.
Non Final Office Action, Mail Date Mar. 20, 2012; U.S. Appl. No. 10/740,721.
“Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design” by Sgrol et al., DAC 2001, Jun. 18-22, 2001, copyright ACM.
“OSI Reference Model—The ISO Model of Architecture for Open Systems Interconnection,” by Zimmermann, IEEE Transactions on Communicaions, Apr. 1980.
“SuperPaint: An Early Frame Buffer Graphics System”, by Richard Shoup, IEEE Annals of the History of Computing, copyright 2001.
“Multimedia Processors” by Kuroda et al., Proceedings of the IEEE, Jun. 1998.
“Test Requirements for Embedded Core-based Systems and IEEE P1500” by Yervant Zorian, International Test Conference, copyright IEEE 1997.
PCI Express Card Electromechanical Specification Rev. 1.1, 2005, p. 87.
A parallel algorithm for polygon rasterization Juan Pineda Jun. 1988 ACM.
A VLSI architecture for updating raster-scan displays Satish Gupta, Robert F. Sproull, Ivan E. Sutherland Aug. 1981 ACM SIGGRAPH Computer Graphics, Proceedings of the 8th annual conference on Computer graphics and interactive techniques SIGGRAPH '81, vol. 15 Issue 3 Publisher: ACM Press.
Blythe, OpenGL Section 3.4.1, “Basic Line Segment Rasterization”, Mar. 29, 1997, pp. 1-3.
Boyer, et al.; “Discrete Analysis for Antialiased Lines,” Eurographics 2000; 3 Pages.
A hardware assisted design rule check architecture Larry Seiler Jan. 1982 Proceedings of the 19th conference on design automation DAC '82 Publisher: IEEE Press.
Foley, J. “Computer Graphics: Principles and Practice”, 1987, Addison-Wesley Publishing, 2nd Edition, p. 545-546.
Fuchs; “Fast Spheres Shadow, Textures, Transparencies, and Image Enhancements in Pixel-Planes”, ACM; 1985; Department of Computer Science, University of North Carolina at Chapel Hill, Chapel Hill, NC 27514.
Related Publications (1)
Number Date Country
20080106328 A1 May 2008 US
Divisions (1)
Number Date Country
Parent 10942209 Sep 2004 US
Child 12005691 US