Claims
- 1. A semiconductor dynamic memory device of three-dimensionally stacked structure comprising
- a first active layer which is flat and is formed on a single crystalline silicon substrate,
- a second active layer which is flat and is obtained by melting polycrystalline silicon by irradiation on an insulative layer which electrically insulates said first active layer from said second active layer, and
- throughholes connecting said active layers across said insulative layer,
- each of said active layers comprising single crystalline active element areas which serve to have transistors formed therein, separation areas which individually insulate said active element areas and passive element areas which serve to have plane capacitors, said active element areas and said separation areas having selected widths, PMOS, NMOS or CMOS field effect transistors being formed in said active element areas of each of said active layers, plane capacitors being formed in said passive element areas of each of said active layers, each of said transistors in said first active layer being connected to one of said plane capacitors in said second active layer through one of said throughholes and each of said transistors in said second active layer being connected to one of said plane capacitors in said first active layer through another of said throughholes.
- 2. The semiconductor dynamic memory device of claim 1 wherein said first active layer is of SOI structure obtained by melting polycrystalline silicon by irradiation on another insulative layer on said substrate.
- 3. The semiconductor dynamic memory device of claim 1 further comprising a redundant circuit section contained in said first active layer and/or said second active layer.
- 4. The semiconductor dynamic memory device of claim 1 further comprising a test circuit for testing the functions originally intended for said active elements, and redundant circuits for said test circuit, said test circuit and said redundant circuits being contained in said first active layer or said second active layer.
- 5. The semiconductor dynamic memory device of claim 1 wherein said active layers are stacked one on top of another and said element comprises throughholes which connect said layers in perpendicular direction.
Priority Claims (4)
Number |
Date |
Country |
Kind |
61-8575 |
Jan 1986 |
JPX |
|
61-8576 |
Jan 1986 |
JPX |
|
61-11542 |
Jan 1986 |
JPX |
|
61-24577 |
Feb 1986 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 001,953, filed Jan. 8, 1987, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4485459 |
Vehkateswaran |
Nov 1984 |
|
4489478 |
Sakurai |
Dec 1984 |
|
Non-Patent Literature Citations (2)
Entry |
Sturm et al., IEEE Electron Device Letters, vol. EDL5, No. 5, May 1984, pp. 151-153. |
Akiyama et al., IEEE International Electron Device Meeting, Dec. 3, 1983, Technical Digest, pp. 352-355. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
1953 |
Jan 1987 |
|