A semiconductor evaluation device according to a first embodiment of the present invention and an evaluation method using the semiconductor evaluation device will be described with reference to the drawings.
In
The gate electrode GE1 has gate contacts GC1 formed at the respective end portions of the first and second gate portions GEx and GEy, each of which is connected to a metal pad via a metal wire not shown. At the time of measurement, a gate voltage is applied to each of the gate contacts GC1 from an external measurement apparatus via the metal pad and the metal wire. The gate contact GC1 may also be provided only on either one of the first and second gate portions GEx and GEy.
Contacts DC1, DC2, DC3, and DC4 are formed on the respective impurity diffusion regions of the impurity diffusion layer D1 which serve as the source/drain regions. The contacts DC1 to DC4 are connected individually to metal pads MP1, MP2, MP3, and MP4 by metal wires. A source voltage or a drain voltage is applied to each of the metal pads MP1 to MP4 or, alternatively, each of the metal pads MP1 to MP4 is placed in an electrically unconnected floating state.
In the first embodiment, n (n is an integer of 2 or more) semiconductor evaluation device are prepared by stepwise displacing the gate electrode GE1 in the semiconductor evaluation device having a gate pattern as shown in
A description will be given herein below to an evaluation method using the plurality of semiconductor evaluation device having the patterns in which the gate electrode GE1 described above has been displaced in fifteen different ways with reference to the flow chart of
First, as shown in Step ST01 of
The drain saturation current of each of the transistors is represented by the following numerical expressions:
Idsat(W/2+ΔW)=idsat·W/2+idsat·ΔW+δ (1)
Idsat(W/2−ΔW)=idsat·W/2−idsat·ΔW+δ (2)
wherein the left sides are functions of the gate width W, idsat represents a drain saturation current per unit gate width, and each of δ, δ′ represents an extremely small current flowing in the area of the semiconductor region R1 which is located under the intersecting portion of the gate electrode GE1.
Next, as shown in Step ST02, the difference between the drain saturation currents represented by the numerical expressions (1) and (2) is calculated to increase the sensitivity of each of the drain saturation currents related to ΔW, which is represented by the following numerical expression (3):
wherein the difference (δ−δ′) between the extremely small currents is approximated to 0.
Next, as shown in Step ST03 and
Judging from the numerical expression (3), if the amount of mask misalignment is zero, ΔIdsat=0 should be satisfied when ΔW=0 is satisfied. However, since misalignment occurs in an actual fabrication process, i.e., since misalignment occurs when a mask having a design pattern for the semiconductor region R1 serving as the active region surrounded by the isolation region 10 is aligned with another mask having a design pattern for the gate electrode GE1, the straight line 1 representing actually measured values given by ΔIdsat and ΔW does not pass through the origin, as shown in
Although the first embodiment has used the drain saturation currents Idsat as the electric characteristics of the transistors, the electric characteristics of the transistors need not be limited to the drain saturation currents. Misalignment can also be evaluated even when drain currents in linear regions and other electric characteristics are used.
Next, as shown in Step ST04, the intercept (X-axis intercept of
If it is assumed that the relationship represented by ΔIdsat=A·ΔW+B (wherein A and B are constants) is satisfied, the amount X of mask misalignment can be determined from the following numerical expression (4):
Amount X of Misalignment=−B/A (4).
Next, as shown in Step ST05, it is assumed that the X-axis intercept of
Thus, in the first embodiment, the amount of mask misalignment can be evaluated from the correlations between the amounts of displacement of the single gate electrode GE1 and the differences between the electric characteristics of the four MISFETs by preparing the plurality of evaluation patterns in each of which the gate electrode GE1 having the cross-shaped plan configuration is displaced from the center position of the semiconductor region R1 by a different amount of displacement.
In addition, the use of the gate pattern having the cross-shaped plan configuration for the gate electrode GE1 allows simultaneous evaluation of the amounts of mask misalignment in the X-axis direction and in the Y-axis direction.
The accuracy of measuring the amount X of mask misalignment will be estimated therein below. A standard deviation δΔIdsat showing variations in each ΔIdsat due to impurity fluctuations is represented by the following numerical expression (5):
δΔIdsat=√2·P/√(Lg·W) (5)
wherein P is the Pelgrom coefficient of a saturation current (see, e.g., IEEE J. Solid-State Circuits, Vol. 24, pp. 1433-1440 (1989)).
The standard deviation δx of the ΔW-axis intercept of the regression line ΔIdsat=A·ΔW+B is given by the following numerical expression (6):
δx2=δA2/B2+A2·δB2/B4 (6)
wherein δA and δB are the respective standard deviations of the gradient A and the intercept B, which can be represented by the following numerical expressions (7), (8), and (9) (see, e.g., “Data Reduction and Error Analysis,” McGraw-Hill, pp. 109-110, (2003)):
δA=δΔIdsat·√(Σx2/Δ) (7)
δB=δΔIdsat·√(N/Δ) (8)
Δ=N·Σx2−(Σx)2 (9)
wherein N is the number of data pairs (ΔW, ΔIdsat) used to determine the regression line. The use of the numerical expressions shown above can achieve a measurement accuracy of 3 nm with 3δ when, e.g., transistors each satisfying W/Lg=1/0.7 μm are used.
Although the number N of data pairs has been assumed to be 15 in the first embodiment, it is not limited thereto. For example, it is sufficient for the number N of data pairs to be 2 or more and preferably 3 or more.
In Document 1 described above, the use of transistors each satisfying W/Lg=0.8/2.4 μm and a measurement accuracy of 6.5 nm 3δ are reported. In addition, since no consideration has been given to variations in the drain saturation current Idsat due to impurity fluctuations, it is expected that an error is not less than the reported value. Moreover, in the evaluation method disclosed in Document 1, the evaluation pattern in the vertical (Y-axis) direction is different from the evaluation pattern in the horizontal (X-axis) direction. As a result, there is a possibility that the electric characteristics of the evaluation pattern in the vertical direction are undesirably different from those of the evaluation pattern in the horizontal direction under the influence of a stress, an optical proximity effect, or the like
A second embodiment of the present invention will be described herein below with reference to the drawings.
First, in Step ST10 shown in
In the second embodiment, the relationship between the actual amount X of misalignment and the difference ΔIdsat between drain saturation currents is derived in a tabular form (as a table) or as a function. Specifically, in the semiconductor evaluation device shown in
Next, in Step ST11 shown in
Next, in Step ST12, the difference ΔIdsat between the drain saturation currents of the pair of measured transistors is calculated.
Next, in Step ST13, an amount of mask misalignment can be determined from the preliminarily derived function shown in
Thus, according to the second embodiment, the amount of misalignment of the mask for the gate electrode GE1 can be easily evaluated by, e.g., preliminarily calculating the relationship between the amount of mask displacement between the pair of transistors and the difference between the drain saturation currents as an exemplary electric characteristic by simulation or the like and then performing actual measurement at least once afterwards.
Moreover, since the second embodiment has used the gate pattern having the cross-shaped plan configuration for the gate electrode GE1 composing each of the MISFETs in the semiconductor evaluation device, mask misalignment in the X-axis direction and mask misalignment in the Y-axis direction can be evaluated simultaneously.
Although the evaluation method is easier in the second embodiment than in the first embodiment, the accuracy of evaluation is higher in the first embodiment.
A third embodiment of the present invention will be described herein below with reference to the drawings.
More specifically, in the first and second semiconductor evaluation device 31 and 32 shown in the partially enlarged view of
The contact DC1 on the impurity diffusion layer D1 in the first semiconductor evaluation device 31 and the contact DC4 on the impurity diffusion layer D1 in the second semiconductor evaluation device 32 are connected to the individual drain terminals D via the first decoder circuit 21.
The contact DC2 on the impurity diffusion layer D1 in the first semiconductor evaluation device 31 and the contact DC3 on the impurity diffusion layer D1 in the second semiconductor evaluation device 32 are connected to a source terminal S.
In the case of using the evaluation method according to the first embodiment, the amounts of displacing the respective gate electrodes GE1 of the first and second semiconductor evaluation device 31 and 32 for obtaining a plurality of data pairs (ΔW, ΔIdsat) are set to the same values.
As a result, measurement equivalent to that when performed with respect to one pair of MISFETs included in the first semiconductor evaluation device 31 can be performed by using one MISFET in the first semiconductor evaluation device 31 and one MISFET in the second semiconductor evaluation device 32 without causing the problem of a leakage current or the like.
By further using so-called on-chip logic circuits integrated on a semiconductor substrate, such as the first and second decoder circuits 21 and 22, it is possible to improve the integration density of the plurality of semiconductor evaluation device and reduce a measurement time.
By forming the plurality of semiconductor evaluation device each having the same patterns and averaging the electric characteristics of the individual MISFETs, it is possible to further improve the accuracy of evaluating the amount of mask misalignment by reducing measurement variations.
Thus, the semiconductor evaluation device according to the present invention and the evaluation method using the same allow prompt and high-accuracy electric evaluation of an amount of misalignment between the active region of a transistor and a gate electrode at an arbitrary position on a wafer (chip) and are therefore useful for a semiconductor evaluation device for electrically evaluating an amount of mask misalignment in process steps for fabricating a semiconductor device or the like.
Number | Date | Country | Kind |
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2006-129073 | May 2006 | JP | national |