The present invention relates to a semiconductor fabrication method, and in particular to a semiconductor fabrication method in which thermal oxidation is performed with dummy wafers.
Thermal oxidation is one of the most common processes in semiconductor fabrication. Normally, thermal oxidation is performed in a furnace, where dummy wafers are introduced to reduce the loading effect and to improve the uniformity by thermal oxidation. Now refer to
The present invention provides a semiconductor fabrication method using silicon nitride-coated dummy wafers, which may reduce dummy wafer consumption and avoid generation of particulate matter.
The present invention provides a semiconductor fabrication method, including:
In the method according to the present invention, the thermal oxidation tool may be a thermal oxidation furnace.
In the method according to the present invention, the protective layer may be a silicon nitride film; the silicon nitride film may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD); preferably, the silicon nitride film is formed by Low-pressure CVD (LPCVD) at the temperature of 760° C.
In the method according to the present invention, the protective layer may have a thickness ranging from 500 Å to 1000 Å.
The present invention has the advantages that: a protective layer is deposited on the dummy wafer such that the protective layer fully encases the dummy wafer; consequently, the dummy wafer will not be oxidized during thermal oxidation, which may reduces dummy wafer consumption, decreases production cost, avoids particulate matter produced due to oxidation of the dummy wafer, and prevents the wafer to be oxidized from contamination.
Technical features and effects of the technical solution of the invention will be described in details hereinafter with reference to the accompanying drawings in connection with the exemplary embodiments.
First, wafers to be oxidized 12, dummy wafers 10 and monitor wafers 11 are provided. In the case where the wafers to be oxidized 12 cannot fill up the thermal oxidation tool, a certain amount of dummy wafers 10 have to be introduced in the thermal oxidation tool, so that the wafers in whole would fill up the thermal oxidation tool, to avoid the loading effect and to have the wafers oxidized equally throughout the thermal oxidation tool and between batches. Reference can be made to
Before loading the wafers into the thermal oxidation tool to perform thermal oxidation, a protective layer 13 is deposited on the outer surface of the dummy wafer 10 such that the protective layer 13 fully encases the dummy wafer 10, as shown in
Next, the wafers to be oxidized 12, the dummy wafers 10 and the monitor wafers 11 are arranged in the thermal oxidation tool, to perform thermal oxidation. The thermal oxidation tool may be a thermal oxidation furnace; and a monitor wafer 11 may be positioned in each of the upper, middle and lower sections of the furnace, for monitoring the process in the sections of the furnace.
When the thermal oxidation is over, the wafers are pulled out of the thermal oxidation tool, among which, the wafers to be oxidized 12 will go through subsequent processing processes, to form desired semiconductor devices; and the dummy wafers 10 can be used again, because they are not oxidized due to the protection by the protective layer 13.
Therefore, in the invention, a protective layer 13 is deposited on the dummy wafer 10 such that the protective layer 13 fully encases the dummy wafer. Being protected by the protective layer 13, the dummy wafer is not oxidized during thermal oxidation; consequently, the hydrometallurgy process for removing the silicon oxide in the prior art is no longer necessary. Hence, dummy wafer consumption is reduced, production cost is decreased, particulate matter produced due to oxidation of the dummy wafer 10 is avoided, and the wafer to be oxidized is prevented from contamination.
The present invention is described above in connection with the exemplary embodiments. It should be noted that a variety of alternations and equivalents may be made to the technical solution of the invention by those skilled in the art without deviation from the scope of the invention. In addition, many situation-specific and material-specific modifications can be made based on the disclosure herein. Therefore, the embodiments disclosed herein are for exemplary purpose only and should not be interpreted as limiting the scope of the invention.
Number | Date | Country | Kind |
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201110077477.6 | Mar 2011 | CN | national |
This application is a Section 371 national stage application of International Application No. PCT/CN2011/072584 filed on Apr. 11, 2011, which claims priority to CN201110077477.6 filed on Mar. 29, 2011, the contents of which are incorporated herein by reference in their entirety.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/CN11/72584 | 4/11/2011 | WO | 00 | 6/17/2011 |