1. Field of the Invention
The present invention relates to a semiconductor integrated circuit that supplies and controls clock signals and to a method for manufacturing the semiconductor integrated circuit.
2. Description of the Related Art
Most of semiconductor integrated circuits containing logic circuits operate by synchronizing with clock signals supplied from outside or clock signals generated inside thereof based on signals supplied form outside. In general, a semiconductor integrated circuit comprises a plurality of flip-flops and a circuit for (referred to as a clock circuit hereinafter) which generates clock signals to be supplied to each flip-flop based on supplied clock signals. In order for the semiconductor integrated circuit to operate properly, it is necessary to supply the clock signals properly to each flip-flop.
Further, in order to reduce power consumption of the semiconductor integrated circuit, it is effective to stop supply of the clock signal for the circuit block that is not to be in action. Thus, there are inserted circuits (clock control circuits) in the clock circuit for stopping supply of the clock signals. The semiconductor integrated circuit is so designed that a section where propagation of the clock signal is stopped changes by switching the clock control circuits for each operation mode.
Furthermore, in accordance with advanced micronization of the semiconductor integrated circuits, size of transistors constituting logic cells contained in the clock circuit have been reduced. Thus, delay time fluctuation due to aging deterioration cannot be ignored.
The aging deterioration of the transistor exhibits a large fluctuation at an initial stage, and the fluctuation amount decreases thereafter. Thus, while the transistor is set in action (gate is ON, low potential for the case of P-channel transistor and high potential for the case of N-channel transistor), burn-in processing (abbreviated as BI processing hereinafter) is performed for deteriorating the transistor before actual use. Such deterioration processing performed before actual use is referred to as advance deterioration hereinafter.
By deteriorating each transistor in advance, fluctuation due to the aging deterioration thereafter becomes insignificant. By checking the circuit action in this state and then shipping it as a product, troubles due to aging deterioration to be happened on the market can be prevented.
However, in order to achieve low power consumption of the semiconductor integrated circuit, the number of the clock control circuits to be inserted has become great and the structure thereof has become complicated. As a result, it is difficult to form an operation mode for propagating the clock signals to all the paths within the clock circuit. Thus, when the BI processing is performed under the state where the clock signal is not propagated, sufficient advance-deterioration processing cannot be performed on a section where the transistor is not in action (gate is OFF). As a result, the product on the market, which is action-tested under the state where there still remains the transistor without sufficient advance-deterioration processing performed by the BI processing, may deteriorate over time due to actual operation and generate a large delay time fluctuation. Therefore, there may cause failure when used by a user.
In order to perform sufficient BI processing for the case of complicated circuit, the BI processing may be performed for each of a plurality of operation modes. By performing the BI processing for each of the plurality of operation modes, the PI processing can be performed while all the transistors within the clock circuit are in action. However, there generate other problems, i.e. an increase in the time for performing the BI processing and an increase in the inspection cost.
For those problems, Japanese Patent Unexamined Publication (6-325597) discloses a method for applying stress for shortening the time for performing the BI processing of the memory circuit through transmitting boosted signals to gate oxide films of all the memory-cell transistors within a chip.
The conventional method as described is a method that applies stress for each memory cell lined in array like the memory circuit through multiple-selection of word lines that are directly connected to each memory cell by BI signals. However, there is no such signal lines like the word lines directly connected to each cell in a random logic such as a clock signal, in which a buffer, inverter, clock control circuit, etc. are in serial-connection. Therefore, this method is not applicable. Furthermore, when the BI signal is connected to each cell as in the conventional case, wirings for connection becomes enormous. Thus, it is not practical. Moreover, the conventional method supplies stress to each cell by changing row address lines, so that it requires the time for processing, which is proportional to the number of the row address lines.
The main object of the present invention therefore is to perform BI processing (advance deterioration) uniformly on all the transistors without increasing the processing time and the wirings.
In order to achieve the aforementioned object, the semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling propagation of the clock signal. The clock control circuit comprises a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state of the clock circuit when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal. The clock control circuit controls propagation of the clock signal outputted from the clock control signal output terminal based on the burn-in control signal inputted to the burn-in control signal input terminal.
A typical example of the semiconductor integrated circuit manufacturing method according to the present invention comprises the steps of: preparing a plurality of clock control circuits which comprise a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal; and connecting the plurality of clock control circuits successively on a circuit by repeating processing, which is to connect the burn-in control signal output terminal of one of the plurality of clock control circuits to the burn-in control signal input terminal of another circuit.
In the semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method of the present invention, propagation of the clock signal in the clock control signal output terminal of the clock control circuit is controlled by inputting the burn-in control signal to the burn-in control signal input terminal of the clock control circuit. With this, all the transistors can be advance-deteriorated. Also, one-time processing allows the transistors to be advance-deteriorated, thus increasing no processing time. Furthermore, the burn-in control signal input terminal and the wiring are added only to the clock control circuit, so that an increase of the wiring can be suppressed.
Moreover, by changing the signal-fixed direction, all the transistors can be advance-deteriorated without increasing the processing time and the wirings. Also, one-time processing allows the transistors to be advance-deteriorated, thus increasing no processing time.
Furthermore, with the semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method of the present invention, all the transistors in the clock circuit that supplies and controls the clock signals can be advance-deteriorated without increasing the processing time and the wirings.
Other objects of the present invention will become clear from the following description of the preferred embodiments and the appended claims. Those skilled in the art will appreciate that there are many other advantages of the present invention possible by embodying the present invention.
Preferred embodiments of the present invention will be described hereinafter by referring to the accompanying drawings.
A first embodiment of the present invention will be described by referring to
In
In
In the circuit of
In the meantime, when the clock signal to the rise signal action flip-flop 106 is supplied, by making the clock control signal 101 as high potential, waveform of the clock signal 100 propagates to an output signal of the AND circuit 103. As a result, the transistors (hereinafter, referred to as a flip-flop driven-state operating transistor) which operate when the rise signal action flip-flop 106 obtains data are the transistors 119, 120, 118, 122, and 125.
Particularly, after the AND circuit 103, the clock-signal non-supplied-state operating transistors 123, 124 and the flip-flop driven-state operating transistors 122, 125 differ. Thus, when the BI processing is performed while the AND circuit 103 is under the state where supply of the clock signal is stopped, the flip-flop driven-state operating transistors 122, 125 cannot be advance-deteriorated. As a result, in the clock circuit connected to the rise signal action flip-flop 106, the transistors 122 and 125, after being on the market, may face aging deterioration when the clock circuit is in action, and the circuit may malfunction.
Thus, the AND circuit 103 is replaced with the clock control circuit 304 with BI control signal input terminal. As shown in
When supply of the clock signal to the rise signal action flip-flop 106 in the clock circuit of
As described above, in the semiconductor integrated circuit to which the clock control circuit 304 with BI control signal input terminal is mounted, the flip-flop driven-state operating transistors 122 and 125 can be advance-deteriorated even under the state where supply of the clock signal is stopped. Thereby, all the transistors can be advance-deteriorated without causing any increase in the processing time and the wirings.
The above-described structure of the clock control circuit 304 with BI control signal input terminal is merely an example. In this case, as shown in
Furthermore, regardless of the structures and conditions, any of the following controls may be carried out. The output of the clock control signal output terminal (Z) 330 is set:
As described above, by setting the state of the output terminal elective from high potential, low potential, or the output of the clock signal waveform, any transistors can be advance-deteriorated. Specifically, constant output of the high potential from the clock control circuit with BI control signal input terminal allows supply of continuous electric charge to P-channel-type transistors that affect the drive of the rise signal action flip-flop. Thus, it is possible to promote advance-deterioration of the P-channel-type transistors within a short period.
Furthermore, constant output of the low potential from the clock control circuit with BI control signal input terminal allows supply of continuous electric charge to N-channel-type transistors that affect the drive of the fall signal action flip-flop. Thus, it is possible to promote advance-deterioration of the N-channel-type transistors within a short period.
Moreover, constant output of the clock waveform from the clock control circuit with BI control signal input terminal allows advance-deterioration of the P-channel-type and N-channel-type transistors to the same extent as that of the clock circuit which has no clock control circuit inserted therein.
A second embodiment of the present invention will be described by referring to
In
The clock circuit shown in
In order to overcome such congestion of the wiring, in the embodiment, the clock control circuits 304 with BI control signal input terminal are replaced with the clock control circuits 500 with BI control signal input/output terminal shown in
In the clock circuit comprising the clock control circuits 500 with BI control signal input/output terminal (
The input part of the BI control signal 400 in the semiconductor integrated circuit, along with the clock control circuits 500 with BI control signal input/output terminal, is designed to be disposed on the semiconductor integrated circuit in advance. Further, the BI control signal 400 is a signal for sufficiently advance-deteriorating the transistors. Thus, there is no restriction in the transmission speed thereof so that there is no problem caused by chain-connection in terms of the signal transmission speed.
Next, there is described the method of chain-connecting the clock control circuits 500 with BI control signal input/output terminal in the clock circuit by referring to
Then, the clock control circuits or the clock control circuits 304 with BI control signal input terminal 304 on the clock circuit, which are found in the step 700, are replaced with the clock control circuits 500 with BI control signal input/output terminal (clock control circuit replacing step 701).
Subsequently, in the chain connecting step 702, the control signal input terminals (C) 302 of each clock control circuit 500 with BI control signal input/output terminal and the BI control signal output terminal (SO) 501 are chain-connected in order (chain connecting step 702).
When replacing with the clock control circuits 500 with BI control signal input/output terminal in the clock control replacing step 701, there are prepared and replaced with the clock control circuits 500 with BI control signal input/output terminal 500 having the same delay value, respectively, as that of the clock control circuits as the target of replacement. Thereby, generation of clock skew due to the replacement can be suppressed.
However, in the procedure shown in
Therefore, it is more preferable to perform the procedure shown in
First, in the clock control circuit finding step 700, the clock control circuit replacing step 701, and the chain-connecting step 702, each step is performed in the same manner as that of
By repeating the step 704 described above, the input part of the BI control signal 400 of the semiconductor integrated circuit, the control signal input terminals (C) 302 of each clock control circuit 500 with BI control signal input/output terminal, and the BI control signal output terminals (SO) 501 can be reconnected via the shortest route.
In the semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method constituted as described above, the clock control circuits 500 with BI control signal input/output terminal are disposed on the clock circuit and, then, the input part of the BI control signal 400, the BI control signal input terminals (C) 302 of each clock control circuit 500 with BI control signal input/output terminal, and the BI control signal output terminals (SO) 501 are connected to each other (chain connection) to have the shortest connecting route. With this, all the transistors can be advance-deteriorated without increasing the processing time and the wiring. In addition, it is possible to decrease congestion of the wiring in the BI control signal wiring 406 and the length of the wiring.
The described structure of the clock control circuit 500 with BI control signal input/output terminal is merely an example. As shown in
The buffer circuit 502 is used for connecting between the BI control signal input terminals (C) 302 of the clock control circuit 500 with BI control signal input/output terminal and the BI control signal output terminals (SO) 501. However, the inverter circuit may be used instead and the logic is inverted for being propagated.
That is, when the following conditions are satisfied;
In such case, for making the BI control signal appropriate for the advance-deterioration of the fall signal action flip-flop, the logic of signal propagated from the BI control signal input terminal (C) 302 to the BI control signal output terminal (SO) 501 may be inverted by the inverter circuit. With this, all the rise signal action flip-flops and the fall signal action flip-flops on the clock circuit can be advance-deteriorated.
In
Further, the clock control circuits 500 with BI control signal input/output terminal (
Furthermore, in the connecting method described by referring to
Moreover, the output part 600 of the BI control signal shown in
A third embodiment of the present invention will be described by referring to
In
The manufacturing method illustrated in
Then, simulations for each operation modes are carried out on the circuit that has completed the CTS step 800 so as to measure the operation rate of the clock circuit. Then the toggle-rate measuring step 801 is performed. By measuring the toggle rate, the mode with the highest operating rate (referred to as a first operation mode hereinafter) is judged.
Next, in the replacing-target clock control circuit judging step 802, there is obtained information regarding the clock control circuit that does not operate at the time of the first operation mode and information regarding the clock control circuit where the clock signal is fixed by the clock control signal.
Based on the result of the step 802, in the clock control circuit replacing step 803, only the clock control circuit where the signal is fixed under the first operation mode is replaced with the clock control 304 circuit with BI control signal input terminal or the clock control circuit 500 with BI control signal input/output terminal. By designing the clock control circuits 304 with BI control signal input terminal and the clock control circuits 500 with BI control signal input/output terminal to have the same delay value as that of the clock control circuit having no BI control input signal, generation of clock skew after the replacement can be prevented.
After completing the replacement in this manner, the BI processing is performed in the BI step 804. The BI mode when performing the BI processing is the BI mode that includes an operating condition of the first operation mode and an operating condition for outputting a desired signal from the clock control circuit 304 with BI control signal input terminal or the clock control circuit 500 with BI control signal input/output terminal.
Next, there is described the designing procedure shown in
Then, the wiring step 805 is performed considering the influence of the wiring congestion due to the use of the clock control circuits 304 with BI control signal input terminal or the clock control circuits 500 with BI control signal input/output terminal. In the wiring step 805, each of the circuits such as the AND circuit, buffer circuit, etc. are wired (connected by wiring) physically according to a connecting rule. After the wiring, the degree of wiring congestion is calculated. The degree of the wiring congestion can be calculated from the number of passing wirings per unit area, etc. for example.
Subsequently, as in
With the second operation mode detected in the toggle-rate measuring step 806, the replacing-target clock control circuit judging step 807 is performed. By the step 807, there is obtained information regarding the clock control circuit that does not operate and information regarding the clock control circuit where the clock signal is fixed by the clock control signal.
Based on the result of the step 807, in the clock control circuit replacing step 808, only the clock control circuit where the signal is fixed under the second operation mode is replaced with the clock control circuit 304 with BI control signal input terminal or the clock control circuit 500 with BI control signal input/output terminal. By designing the clock control circuit 304 with BI control signal input terminal and the clock control circuit 500 with BI control signal input/output terminal to have the same delay value as that of the clock control circuit having no BI control input signal, generation of clock skew after replacement of the circuits can be prevented.
After completing the replacement in this manner, the BI processing is performed in the BI step 809. The BI mode when performing the BI processing is the BI mode that includes an operating condition of the second operation mode and an operating condition for outputting a desired signal from the clock control circuit 304 with BI control signal input terminal or the clock control circuit 500 with BI control signal input/output terminal.
The semiconductor integrated circuit manufacturing method structured as described above enables the following effects. With the manufacturing procedure shown in
The wiring of the BI control signal may be chain-connected (includes the case with branches) as shown in
A fourth embodiment of the present invention will be described by referring to
When supply of the clock signal to the rise signal action flip-flop 106 is stopped in the structure of the clock circuit as shown in
In the meantime, at the time of supplying the clock signal to the rise signal action flip-flop 106, the clock signal is set as high potential so that the waveform of the clock signal 100 is propagated to the output signal of the AND circuit 103. As a result, the transistors 122 and 125 become the flip-flop driven-state operating transistors.
As described, the clock-signal non-supplied-state operating transistors, 123, 124 and the flip-flop driven-state operating transistors 122, 125 are different. Therefore, when the BI processing is performed under the state where supply of the clock signal to the AND circuit 103 is stopped, the flip-flop driven-state operating transistors 122, 125 cannot be advance-deteriorated. As a result, in the clock circuit to the rise signal action flip-flop 106, the transistors 122 and 125 may be advance-deteriorated when the clock circuit is in action after being on the market and the circuit may malfunction.
Thus, the structure of the clock control circuit is modified by the procedure shown in
The procedure shown in
In the step 901, the clock-signal non-supplied-state operating transistors, 123, 124 are detected when the output signal of the AND circuit 103 is fixed low and supply of the clock signal to the rise signal action flip-flop 106 is stopped. In the clock circuit, the transistors inside the AND circuit 103 of the clock control circuit are eliminated form the detection target as the operating transistors.
In the step 902, it is detected that the clock-signal non-supplied-state operating transistors, 123, 124 and the flip-flop driven-state operating transistors 122, 125 are different.
In the step 903, in order to change the signal fixed direction of the clock control circuit (AND circuit 103) from low potential to high potential, the circuit structure is modified in such manner that the AND circuit 103 is changed to the OR circuit and, at the same time, the inverter circuit is inserted between the AND circuit 103 and the input part of the clock control signal.
By the modification of the circuit structure performed in the step 903, as shown in
With the semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method constituted as described above, the flip-flop driven-state operating transistors can be advance-deteriorated even if the BI processing is performed under the state where supply of the clock signal is stopped. Therefore, all the transistors can be advance-deteriorated without increasing the processing time and the wirings.
A fifth embodiment of the present invention will be described by referring to
In the clock circuit of
In
Under the state where both the rise signal action flip-flop 106 and the fall signal action flip-flop 1100 are present as described above, the following modifications of the circuit may be performed (see the fourth embodiment) in order to make the clock-signal non-supplied-state operating transistors be consistent with the flip-flop driven-state operating transistors:
Thus, in the step 903 of the method for modifying the clock control circuit illustrated in
The above-described modifications can be easily achieved by performing: the processing of discriminating the rise signal action flip-flop and the fall signal action flip-flop; and the processing of modifying the clock control circuit to the circuit structure that can fix the signal as high potential and to the circuit structure that can fix the signal as low potential in accordance with the action state of the discriminated flip-flop.
Specifically, as shown in
With the semiconductor integrated circuit manufacturing method constituted as described above, it is possible to advance-deteriorate the flip-flop driven-state operating transistors by the BI processing under the clock-signal non-supplied state, even if there both exist, simultaneously, the transistors (the flip-flop driven-state transistors and the like of the rise signal action flip-flop 106), which are different from the clock-signal non-supplied-state operating transistors, and the transistors (the flip-flop drive-state transistors and the like of the fall signal action flip-flop 1100), which are consistent with the clock-signal non-supplied-state operating transistors. In addition, all the transistors can be advance-deteriorated without increasing the processing time and the wirings.
A sixth embodiment of the present invention will be described by referring to
In
In the manufacturing step of the via and the metal wiring, there is required the processing using plasma such as dry etching. For example, when forming the via in an insulating layer, the via and the meal wiring are formed by: adding a resist film on the insulating layer for masking the part other than the via part; eliminating the insulating film of the via part through dry etching, and plasma-injecting a conductive material to the eliminated part. Wiring can be formed through the same processing.
Plasma is used in this step of forming the via and the wiring. However, when the via and the wiring are not connected to a diffusion layer, plasma charges are accumulated in the via and the wiring, and electric current flows into a gate oxide film of the connected transistor. By the electric current flown in this way, there are caused malfunctions such as breakdown of the gate oxide film, changes in the transistor property due to the change in the film quality of the gate oxide film and, furthermore, deterioration in the life of hot-carrier.
Such phenomenon is called “antenna effect”. In general, the malfunction such as the breakdown of the gate oxide film is prevented by setting the antenna effect as a specific value or less. Hereinafter, damage to the gate due to the antenna effect is referred to as “antenna damage”.
However, the state where the electric current is flown into the gate oxide film of the transistor due to the plasma charge is the same as the state where the gate of the transistor is ON. In additions, the plasma processing is performed at high temperatures. Taking such characteristic of the plasma processing into account, by accumulating the proper amount of the plasma charge in the gate oxide film (giving antenna damage) through the plasma processing, it is possible to obtain the same effect (advance-deterioration) as that of aging deterioration of the transistors obtained by the BI processing. Therefore, it becomes unnecessary to perform the advance-deterioration processing by the BI processing for the transistor with the proper value of antenna damage.
Thus, in the embodiment, the amount of the antenna damage in the transistor that requires the advance-deterioration processing is appropriately corrected so that the antenna damage equivalent to the advance-deterioration processing is supplied to the via and the wiring. Thereby, the advance-deterioration becomes unnecessary. The amount of the antenna damage can be easily calculated from the number and shape of the vias, the wiring layer, the wiring pattern, the plasma-processing time, etc.
In the embodiment, the above-described processing is performed by the procedure shown in
In the step 1201, the amounts of the antenna damage to the flip-flop driven-state operating transistors 122 and 125 are detected. In the embodiment, it is assumed that the antenna damage of the transistor 125 is within the proper range for the advance-deterioration and the antenna damage of the transistor 122 is less than the proper value.
In the step 1202, redundant via is inserted to the wiring connected to the transistor 122 that is detected in the step 1201 as having the antenna damage of less than the proper value until the value reaches the proper value as the advance-deterioration.
In the step 1203, if all the operating transistors after the clock control circuit come to have the proper-value antenna damage through the processing till the step 1202, those are eliminated from the target of replacing processing. For the operating transistors as the target of the replacing processing, there is performed one of the replacing processing illustrated in the first to fifth embodiment described above. With this, it is possible in this embodiment to reduce, preferably, eliminate the replacing sections of the clock control circuit completely.
In the semiconductor integrated circuit and the semiconductor integrated circuit manufacturing method constituted as described above, all the transistors can be advance-deteriorated without increasing the processing time and the wirings by correcting the antenna damage of the clock control circuit to be the proper value for the advance-deterioration. In addition, it is possible to reduce the number of the clock control circuits to be replaced, which enables reduction in the cell area and congestion of the wiring.
In the embodiment, the antenna damage is increased by inserting the redundant via as the additional factor for the antenna damage. However, the same effects can be achieved also by adding the redundant wiring.
The present invention has been described in detail by referring to the most preferred embodiments. However, various combinations and modifications of the components are possible without departing from the sprit and the broad scope of the appended claims.
Number | Date | Country | Kind |
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2005-057687 | Mar 2005 | JP | national |