SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS CIRCUIT INSERTING METHOD

Abstract

A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable generator is off, a second circuit whose output frequently changes, an input controller which receives the respective outputs from the second circuit and the Enable generator and passes through the input from the second circuit only when the output from the Enable generator is on, a combination circuit which receives the respective outputs from the first circuit and the input controller, and a memory which receives the output from the combination circuit and is driven by the output from the clock controller.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit device according to a first embodiment of the invention;

FIG. 2 is a block diagram showing an example of a semiconductor integrated circuit device according to a second embodiment of the invention;

FIG. 3 is a block diagram showing an example of a semiconductor integrated circuit device according to a third embodiment of the invention;

FIG. 4 is a block diagram showing an example of a semiconductor integrated circuit device according to a fourth embodiment of the invention;

FIG. 5 is a block diagram showing an example of a semiconductor integrated circuit device according to a fifth embodiment of the invention;

FIG. 6 is a block diagram showing an example of a semiconductor integrated circuit device according to a sixth embodiment of the invention;

FIG. 7 is a block diagram showing an example of a semiconductor integrated circuit device according to a seventh embodiment of the invention;

FIG. 8 is a block diagram showing an example of a semiconductor integrated circuit device according to an eighth embodiment of the invention;

FIG. 9 is a flow chart showing an example of a circuit inserting method according to a ninth embodiment of the invention;

FIGS. 10A to 10D are circuit diagrams each showing a relation between gates and an insertion example of a guarding logic;

FIG. 11 is a flow chart showing an example of a circuit inserting method according to a tenth embodiment of the invention;

FIGS. 12A and 12B are circuit diagrams showing an example of the circuit designed according to the tenth embodiment;

FIG. 13 is a circuit diagram showing an example of the circuit designed according to the tenth embodiment;

FIG. 14 is a flow chart showing an example of a circuit inserting method according to an eleventh embodiment of the invention;

FIG. 15 is a flow chart showing an example of a circuit inserting method according to a twelfth embodiment of the invention;

FIG. 16 is a flow chart showing an example of a circuit inserting method according to a thirteenth embodiment of the invention;

FIG. 17 is a circuit diagram showing a schematic gated clock circuit;

FIG. 18A shows a RTL description and FIG. 18B shows an example of a gated clock circuit according to the RTL description shown in FIG. 18A;

FIG. 19 is a drawing for use in describing the situation of the gated clock technique; and

FIG. 20 is a circuit diagram showing a schematic guarding logic circuit.

Claims

1. A semiconductor integrated circuit device comprising: a clock generator which generates a clock signal;an Enable generator which generates an on/off signal;a clock controller which receives an output from the clock generator and an output from the Enable generator and passes through the input from the clock generator only when the output from the Enable generator is on;a first circuit whose output never or seldom changes when the output from the Enable generator is off;a second circuit whose output frequently changes when the output from the Enable generator is off;an input controller which receives the respective outputs from the second circuit and the Enable generator and passes through the input from the second circuit only when the output from the Enable generator is on;a combination circuit which receives the respective outputs from the first circuit and the input controller; anda memory which receives the output from the combination circuit and is driven by the output from the clock controller.

2. The device according to claim 1, wherein the input controller is formed by an AND gate which receives the respective outputs from the second circuit and the Enable generator.

3. The device according to claim 1, wherein the input controller is formed by an OR gate which receives the respective outputs from the second circuit and the Enable generator.

4. The device according to claim 1, wherein the input controller is formed by a latch circuit with Enable signal which receives the output from the second circuit and is controlled by the output from the Enable generator.

5. The device according to claim 1, wherein the first circuit is formed by a feedback loop circuit which connects the output from the memory to the combination circuit as it is.

6. The device according to claim 1, wherein the first circuit is formed by a synchronization circuit which is driven by the output from the clock controller.

7. The device according to claim 1, wherein the first circuit has a second Enable generator which controls a clock of the first circuit, and a period in which the respective outputs of the Enable generator and the second Enable generator are simultaneously off exceeds a threshold.

8. The device according to claim 1, wherein the second circuit has a third Enable generator which controls a clock of the second circuit, a period in which the output of the Enable generator is different from the output of the third Enable generator exceeds a threshold, and an output line from the second circuit to the input controller is connected to another logic circuit within the second circuit.

9. A circuit inserting method comprising: (A) inputting a gate net list designed by a gated clock;(B) exploring a circuit in a tree structure upstream starting from a data input terminal of a flip flop as a starting point, for every flip flop within the gate net list;(C) finding a portion in which a downstream combination circuit does not stop switching only according to the gated clock design, by checking a relation between a driver gate and a load gate from view of each gate found in the tree structure; and(D) in a front stage of the combination circuit, inserting a guarding logic in which an Enable control line of the gated clock of the flip flop as the starting point is input.

10. The circuit inserting method according to claim 9, wherein when a driver gate and a load gate are in a one to many relation from view of each gate found and there exists one load gate or more (not all) such that “every flip flop existing in the downstream path of the output terminal of the load gate is driven by the same clock domain as that of an explore starting flip flop”, of all the load gates loaded by the driver gate, in the process (C),the output terminal of the driver gate is connected to the guarding logic and the output is connected to the input of the load gate.

11. The circuit inserting method according to claim 9, wherein when the driver gate from view of each gate found is the flip flop and the clock domain of the flip flop as the starting point is different from the clock domain of the flip flop as the driver gate, in the process (C),the guarding logic is inserted between an output port of the flip flop as the driver gate and the load gate.

12. The circuit inserting method according to claim 9, wherein, in the process (C), such a condition is added that only when the number of gate stages from the flip flop as the starting point to the driver gate exceeds a threshold.

13. The circuit inserting method according to claim 9, wherein, in the process (C), such a condition is added that only when a delay restriction between the flip flops is satisfied.