Claims
- 1. A semiconductor integrated circuit device comprising:
an integrated circuit provided in a semiconductor chip; and a setting information memory which stores operation/function setting information of said integrated circuit, said setting information memory configured to receive a signal generated based on power-on in reading out said operation/function setting information.
Priority Claims (2)
Number |
Date |
Country |
Kind |
9-42228 |
Feb 1997 |
JP |
|
9-44245 |
Feb 1997 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent application Ser. No. 10/265,728, filed Oct. 8, 2002, which is a continuation of U.S. patent application Ser. No. 09/977,294, filed Oct. 16, 2001, which is a continuation of U.S. patent application Ser. No. 09/527,582, filed Mar. 17, 2000, now U.S. Pat. No. 6,320,428, granted Nov. 20, 2001, which is a divisional of prior U.S. patent application Ser. No. 09/030,915, filed Feb. 26, 1998, now U.S. Pat. No. 6,052,313, granted Apr. 18, 2000, which claims priority under 35 U.S.C. § 119 to prior Japanese Patent Application Nos. 9-42228, filed Feb. 26, 1997 and 9-44245, filed Feb. 27, 1997, the entire contents of which are incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09030915 |
Feb 1998 |
US |
Child |
09527582 |
Mar 2000 |
US |
Continuations (3)
|
Number |
Date |
Country |
Parent |
10265728 |
Oct 2002 |
US |
Child |
10743385 |
Dec 2003 |
US |
Parent |
09977294 |
Oct 2001 |
US |
Child |
10265728 |
Oct 2002 |
US |
Parent |
09527582 |
Mar 2000 |
US |
Child |
09977294 |
Oct 2001 |
US |