Semiconductor integrated circuit device

Abstract

There is disclosed a semiconductor integrated circuit device including a memory cell array having a plurality of blocks, a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer, and a second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer. Regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell. Additional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A and 1B are views showing writing data in a memory cell;

FIG. 2 is a cross-sectional view taken along a bit line direction of memory cells;

FIG. 3A is a view showing a threshold distribution before undergoing the proximity effect, and FIG. 3B is a view showing a threshold distribution after undergoing the proximity effect;

FIG. 4 is a view showing writing data with respect to memory cells;

FIG. 5 is a view showing threshold distributions of memory cells;

FIG. 6 is a circuit diagram showing a first example of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 7 is a view showing an example of a setting of a verify voltage;

FIG. 8 is a view showing threshold distributions before undergoing the proximity effect;

FIG. 9 is a view showing threshold distributions after undergoing the proximity effect;

FIG. 10 is a view showing threshold distributions after additional writing;

FIG. 11 is a circuit diagram showing a second example of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 12 is a circuit diagram showing a third example of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 13 is a circuit diagram showing the third example of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 14 is a block diagram showing a schematic configuration of a NAND type flash memory;

FIG. 15 is a view showing an example of a memory cell array;

FIG. 16 is an equivalent circuit diagram showing an example of a block;

FIG. 17 is a view showing a first example of a writing method according to a second embodiment of the present invention;

FIGS. 18A to 18C are views showing threshold distributions obtained by using an operation method according to a second embodiment of the present invention;

FIGS. 19A to 19C are views showing threshold distributions obtained by using an operation method according to a reference example of the second embodiment of the present invention;

FIG. 20 is a view showing a second example of a writing method according to the second embodiment of the present invention;

FIG. 21 is a view showing a third example of the writing method according to the second embodiment of the present invention;

FIG. 22 is a view showing a fourth example of the writing method according to the second embodiment of the present invention;

FIG. 23 is an equivalent circuit diagram showing another example of the block;

FIG. 24 is a view showing a first example of a writing method according to a third embodiment of the present invention;

FIG. 25 is a view showing changes in threshold distributions according to the first example of the writing method of the third embodiment (Case 1);

FIG. 26 is a view showing changes in threshold distributions according to the first example of the writing method of the third embodiment (Case 2);

FIG. 27 is a view showing changes in threshold distributions according to the first example of the writing method of the third embodiment (Case 3);

FIG. 28 is a view showing changes in threshold distributions according to the first example of the writing method of the third embodiment (Case 3);

FIG. 29 is a view showing a second example of the writing method according to the third embodiment of the present invention;

FIG. 30 is a view showing changes in threshold distributions according to the second example of the writing method of the third embodiment (Case 1);

FIG. 31 is a view showing changes in threshold distributions according to the second example of the writing method of the third embodiment (Case 2);

FIG. 32 is a view showing a third example of the writing method according to the third embodiment of the present invention;

FIG. 33 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 1);

FIG. 34 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 2);

FIG. 35 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 3);

FIG. 36 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 4);

FIG. 37 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 5);

FIG. 38 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 6);

FIG. 39 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 7);

FIG. 40 is a view showing changes in threshold distributions according to the third example of the writing method of the third embodiment (Case 8);

FIG. 41 is a view showing a part of a memory cell array in which NAND type unit cells are arranged;

FIG. 42 is a view showing threshold distributions; and

FIG. 43 is a view showing an image of changes in currents flowing through cells.

Claims

1. A semiconductor integrated circuit device comprising: a memory cell array having a plurality of blocks;a first non-volatile semiconductor memory cell which is arranged in the memory cell array and has an electric charge storage layer; anda second non-volatile semiconductor memory cell which is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell and has an electric charge storage layer, regular data writing being performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory, additional data writing being executed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell.

2. The device according to claim 1, further comprising: a bit line extending along a bit line direction;a first word line extending along a word line direction crossing the bit line direction; anda second word line extending along the word line direction,wherein the electric charge storage layer of the first non-volatile semiconductor memory cell is capacity-coupled with the first word line, and one end of a current path of the first non-volatile semiconductor memory cell is connected with one end of a current path of the second non-volatile semiconductor memory cell,the electric charge storage layer of the second non-volatile semiconductor memory cell is capacity-coupled with the second word line, and the other end of the current path of the second non-volatile semiconductor memory cell is electrically connected with the bit line, andthe first non-volatile semiconductor memory cell and the second non-volatile semiconductor memory cell are adjacent to each other along the bit line direction.

3. The device according to claim 1, further comprising: a first bit line extending along a bit line direction;a second bit line extending along the bit line direction; anda word line extending along a word line direction crossing the bit line direction,wherein the electric charge storage layer of the first non-volatile semiconductor memory cell is capacity-coupled with the word line, and one end of a current path of the first non-volatile semiconductor memory cell is electrically connected with the first bit line,the electric charge storage layer of the second non-volatile semiconductor memory cell is capacity-coupled with the word line, and one end of a current path of the second non-volatile semiconductor memory cell is electrically connected with the second bit line, andthe first non-volatile semiconductor memory cell and the second non-volatile semiconductor memory cell are adjacent to each other along the word line direction.

4. A semiconductor integrated circuit device comprising: a memory cell array having a plurality of block each including a plurality of pages;a first non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array;a second non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell;a third non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array to be adjacent to the first non-volatile semiconductor memory cell;a fourth non-volatile semiconductor memory cell which has an electric charge storage layer and is arranged in the memory cell array to be adjacent to the second non-volatile semiconductor memory cell;a first bit line extending along a bit line direction;a second bit line extending along the bit line direction;a first word line extending along a word line direction crossing the bit line direction, the electric charge storage layer of the first non-volatile semiconductor memory cell being capacity-coupled with the first word line, one end of a current path of the first non-volatile semiconductor memory cell being connected with one end of a current path of the third non-volatile semiconductor memory cell, the electric charge storage layer of the second non-volatile semiconductor memory cell being capacity-coupled with the first word line, one end of a current path of the second non-volatile semiconductor memory cell being connected with one end of a current path of the fourth non-volatile semiconductor memory cell; anda second word line extending along the word line direction, the electric charge storage layer of the third non-volatile semiconductor memory cell being capacity-coupled with the second word line, the other end of the current path of the third non-volatile semiconductor memory cell being electrically connected with the first bit line, the electric charge storage layer of the fourth non-volatile semiconductor memory cell being capacity-coupled with the second word line, the other end of the current path of the fourth non-volatile semiconductor memory cell being electrically connected with the second bit line,wherein regular data writing is performed with respect to the second non-volatile semiconductor memory cell after regular data writing is carried out with respect to the first non-volatile semiconductor memory cell,regular data writing is performed with respect to the third non-volatile semiconductor memory cell after regular data writing is carried out with respect to the second non-volatile semiconductor memory cell, andadditional data writing is performed with respect to the first non-volatile semiconductor memory cell after regular data writing is carried out with respect to the third non-volatile semiconductor memory cell.

5. The device according to claim 1, wherein a verify voltage used for regular data writing with respect to the first non-volatile semiconductor memory cell is different from a verify voltage used for additional data writing with respect to the first non-volatile semiconductor memory cell.

6. The device according to claim 4, wherein a verify voltage used for regular data writing with respect to the first non-volatile semiconductor memory cell is different from a verify voltage used for additional data writing with respect to the first non-volatile semiconductor memory cell.

7. The device according to claim 1, wherein the additional data writing is carried out after writing in one block in the plurality of blocks is finished or after writing in one page in the plurality of pages is finished.

8. The device according to claim 4, wherein the additional data writing is carried out after writing in one block in the plurality of blocks is finished or after writing in one page in the plurality of pages is finished.

9. The device according to claim 1, wherein, as the additional writing, there are a case where a threshold value of the first non-volatile semiconductor memory is shifted in accordance with data written in the second non-volatile semiconductor memory and a case where a shift of the threshold value is suppressed.

10. The device according to claim 4, wherein, as the additional writing, there are a case where a threshold value of the first non-volatile semiconductor memory is shifted in accordance with data written in the second non-volatile semiconductor memory and a case where a shift of the threshold value is suppressed.

11. The device according to claim 1, wherein, when data stored in the first non-volatile semiconductor memory cell has three or more levels, verify reading at the time of the additional writing sequentially supplies two or more verify voltages corresponding to levels of the data having three or more levels to a word line connected with a gate of the first non-volatile semiconductor memory cell in a state where a bit line electrically connected with one end of the current path of the first non-volatile semiconductor memory is pre-charged.

12. The device according to claim 4, wherein, when data stored in the first non-volatile semiconductor memory has three or more levels, verify reading at the time of the additional writing sequentially supplies two or more verify voltages corresponding to levels of the data having three or more levels to a word line connected with a gate of the first non-volatile semiconductor memory cell in a state where a bit line electrically connected with one end of the current path of the first non-volatile semiconductor memory cell is pre-charged.

13. The device according to claim 2, wherein the first non-volatile semiconductor memory cell and the second non-volatile semiconductor memory cell constitute a NAND type unit cell.

14. The device according to claim 4, wherein the first non-volatile semiconductor memory cell and the third non-volatile semiconductor memory cell constitute a first NAND type unit cell, and the second non-volatile semiconductor memory cell and the fourth non-volatile semiconductor memory cell constitute a second NAND type unit cell.