Patent Application
20070267680
Embodiments of the present invention will now be described with reference to the accompanying drawings. In the following description, the constituent elements having substantially the same function and arrangement are denoted by the same reference numerals through all the drawings.
At first, an explanation will be given of an outline of the present invention. A semiconductor integrated circuit device according to the present invention includes a plurality of N-channel transistors and a plurality of P-channel transistors formed therein. The transistors of one of the N-channel type and the P-channel type are provided with gate isolation structures. The transistors of the other of the N-channel type and the P-channel type are provided with shallow trench isolation (STI) structures.
With this arrangement, the transistors of one channel type receive no STI stress, while the transistors of the other channel type receive STI stress to cause the effect of changing the performance thereof, i.e., a strained silicon effect.
More specifically, where the N-channel transistors are provided with the gate isolation structures, the interiors of the transistors are free from stress in a compression direction applied from STI, and the transistors are thereby prevented from suffering degraded performance. Further, where the P-channel transistors are provided with the STI isolation structures, the interiors of the transistors receive stress in a compression direction applied from STI, and the transistors are thereby improved in performance. In other words, the performance of both of the P-channel and N-channel transistors can be controlled by use of STI stress, so that the performance of both of them is efficiently improved.
It should be noted that, depending on the manufacturing process, an arrangement opposite to that described above may be effective to improve transistors in performance and/or to prevent transistors from suffering degraded performance. In this case, N-channel transistors are provided with STI structures, while P-channel transistors are provided with gate isolation structures.
Further, where P-channel transistors are provided with gate isolation structures, while N-channel transistors are provided with STI structures, the delay characteristic of transistors can be controlled to increase the delay. In this case, a delay cell for adjusting clock skew can be formed to have a delay characteristic with a greater delay, so the size of the delay cell can be smaller.
Further, in this embodiment, STI regions 17 are respectively formed at positions at which the active regions 12 are divided into a plurality of unit portions in the longitudinal direction, e.g., each for every two P-channel transistors. Each pair of a P-channel transistor and an N-channel transistor in the active regions 12 and active regions 15 adjacent to each other are provided with a common gate electrode 18, which is formed through a gate insulating film and extends across the regions 12 and 15.
Further, in this embodiment, dummy gate electrodes 18a for gate isolation are respectively formed at positions at which the active regions 15 are divided into a plurality of unit portions in the longitudinal direction, e.g., each for every two N-channel transistors. The dummy gate electrodes 18a provide gate isolation regions 19 using normally-off transistors.
According to the arrangement described above, the P-channel transistors are provided with STI structures each for every two P-channel transistors. Since the STI regions 17 are present on both side of each of the active regions 12 in the channel-length direction, the channel region of each of the P-channel transistors receives STI stress in a compression direction from a direction perpendicular to the channel region (channel-length direction), and the P-channel transistors are thereby improved in characteristic.
On the other hand, the N-channel transistors are provided with gate isolation structures each for every two gate electrodes 18. Since the active regions 15 are thus arranged, each channel region receives no STI stress in a compression direction from a direction perpendicular to the channel region, i.e., receives no compression stress, and the N-channel transistors are thereby prevented from suffering degraded performance.
Each set of the two-input AND gate circuit 31 and two-input OR gate circuit 32 employs four P-channel transistors and four N-channel transistors. A P-sub region 16 is in contact with a metal interconnection line 30, which is in contact with dummy gate electrodes 18a for normally-off transistors in active regions 15, wherein a ground potential is applied to the dummy gate electrodes 18a. The active regions 15 are isolated from each other by gate isolation regions 19. On the other hand, unit portions formed of active regions 12 are isolated from each other by STI regions 17, and thus no gate isolation structures are formed here.
With this arrangement, the respective P-channel transistors receive stress in a compression direction from the STI regions 17, and the transistors are thereby improved in characteristic. On the other hand, since no STI structures are used to isolate unit portions formed of the active regions 15, the channel regions of the N-channel transistors receive no compression stress from STI regions, and the N-channel transistors is thereby prevented from suffering degraded performance. Consequently, it is possible to improve the two-input AND gate circuit 31 and two-input OR gate circuit 32 in characteristic.
In reverse, where the characteristic of an N-channel transistor needs to be further improved, the width of a unit portion as a part of the active regions 15 of the N-channel transistors is set to be greater than the width of the other unit portions. Further, in accordance with this modification, the width of a unit portion as a part of the active regions 12 of the P-channel transistors is set to be smaller than the width of the other unit portions.
In the semiconductor integrated circuit devices shown in
In the pattern layouts described in the first embodiment, one unit portion from the active regions 12 of P-channel transistors and one unit portion from the active regions 15 of N-channel transistors are used to form one basic cell of a gate array. However, this is not limiting.
In a semiconductor integrated circuit device using standard cells 61 or basic cells 51 prepared as described above, gate isolation structures are used to provide device isolation on the transistors of one of the N-channel type and the P-channel type, while STI structures are used to provide device isolation on the transistors of the other of the N-channel type and the P-channel type, thereby improving transistor performance in a gate array or the like.
According to the embodiments described above, there is provided a semiconductor integrated circuit device comprising a CMOS circuit, which includes N-channel transistors and P-channel transistors, wherein a region isolated by a gate isolation structure contains one or more transistors, and a region isolated by an STI structure contains one or more transistors. One region isolated by an STI structure contains one P-channel transistor used for an inverter circuit or two P-channel transistors used for an AND gate circuit or OR gate circuit. Where the number of transistors contained in one region isolated by an STI structure can be one or more, i.e., the number is changeable, the following advantages are obtained. Specifically, for example, in the case of a CMOS inverter, only one P-channel transistor and one N-channel transistor are used. In this case, unit portions for P-channel transistors are formed each in the minimum size such that one unit portion is formed of one transistor. Further, these unit portions are arranged to receive STI stress. Consequently, it is possible to improve the transistors in performance while decreasing the cell size. On the other hand, for example, in the case of a two-input NAND gate circuit of the CMOS type, two P-channel transistors and two N-channel transistors are required. In this case, each unit portion is formed of two transistors and is arranged to receive STI stress from opposite sides. Consequently, it is possible to improve the transistors in performance while decreasing the cell size.
In the embodiments and modifications described above, P-channel transistors are arranged to receive STI stress in the compression direction at their channel regions, so that the transistors are improved in characteristic. Further, N-channel transistors are provided with gate isolation structures to receive no compression stress from STI at their channel regions, so that the transistors are prevented from suffering degraded performance.
However, depending on the material and/or manufacturing method used in a semiconductor process, an arrangement opposite to that described above may be effective to improve transistors in characteristic. In this case, P-channel transistors are provided with gate isolation structures, while N-channel transistors are provided with STI structures.
In the fourth embodiment, P-channel transistors provided with device isolation by STI structures are combined with P-channel transistors provided with device isolation by gate isolation structures. Further, N-channel transistors provided with device isolation by gate isolation structures are combined with N-channel transistors provided with device isolation by STI structures. These combinations are used to form a delay cell region in which the delay characteristic of transistors is controlled to increase the delay. In this case, a delay cell for adjusting clock skew can be formed to have a delay characteristic with a greater delay, so number of cells used in a delay circuit is decreased as a whole and the cell size can be thereby smaller.
With this arrangement, the channel regions in the first active regions 121 of P-channel transistors receive stress in a compression direction due to STI stress, and the transistors are thereby improved in characteristic. Further, the channel regions in the first active regions 151 of N-channel transistors receive no compression stress due to STI, and the transistors are thereby prevented from suffering degraded performance.
On the other hand, in the delay cell region 71, the channel regions in the second active regions 152 receive STI stress, and the transistors thereby suffer degraded performance. Further, the channel regions in the second active region 122 receive no compression stress from STI, the transistors are degraded in characteristic as compared to a state supplied with STI stress. Accordingly, where a delay cell is formed by use of the delay cell region 71, the delay time can be greater than that obtained by a delay cell formed of normal regions, i.e., the first active region 121 and first active region 151. Consequently, a delay cell for handling clock skew can be formed to have a small cell size and a large delay time.
In this embodiment, the transistor channel width in the active regions of P-channel transistors and the transistor channel width in the active regions of N-channel transistors may be adjusted, as needed, as described in a modification of the first embodiment.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-138019 | May 2006 | JP | national |
