Claims
- 1. A semiconductor integrated circuit device comprising:a processing unit for executing a predetermined processing; a first memory unit for storing data including data required by said processing unit; a second memory unit for storing data including data required by said processing unit; a select signal generation circuit for generating a memory select signal specifying the first and second memory units according to a memory address signal from said processing unit, and transmitting said memory select signal in synchronization with a first clock signal; a select circuit for electrically coupling the first and second memory units selectively to an internal bus in accordance with said memory select signal; and a transfer circuit for transferring data from said processing unit to said select circuit via said internal bus in synchronization with a second clock signal complementary to said first clock signal.
- 2. The semiconductor integrated circuit device according to claim 1, further comprising a delay circuit for delaying an output signal of said select signal generation circuit for transmission to said select circuit.
- 3. The semiconductor integrated circuit device according to claim 1, wherein an output signal of said transfer circuit turns definite after an output signal of said select signal generation circuit turns definite.
- 4. The semiconductor integrated circuit device according to claim 1, wherein the first and second clock signals are two phase, non-overlapping clock signals.
- 5. The semiconductor integrated circuit device according to claim 1, wherein an output signal of said transfer circuit is in a definite state for half a cycle of said second clock signal, and an output signal of said select signal generation circuit is in a definite state for one clock cycle period of said first clock signal.
- 6. The semiconductor integrated circuit device according to claim 1, further comprising a latch circuit, arranged at an output node of said select circuit, for latching data output from said select circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2001-288792 |
Sep 2001 |
JP |
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Parent Case Info
This application is a divisional of application Ser. No. 10/212,789, filed on Aug. 7, 2002, now U.S. Pat. No. 6,690,614, issued on Feb. 10, 2004.
US Referenced Citations (6)
Foreign Referenced Citations (2)
Number |
Date |
Country |
62-232-860 |
Sep 1987 |
JP |
08-023267 |
Jan 1996 |
JP |