Semiconductor integrated circuit

Abstract

A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating power shuttable-down circuits, a power non-shutdown circuit and an input/output circuit having considered the characteristic of an SOI structure, as one example of a semiconductor integrated circuit according to the present invention:

FIG. 2 is a plan view illustrating a planer configuration of the semiconductor integrated circuit according to the present invention;

FIG. 3 is a plan view illustrating a planer configuration of the semiconductor integrated circuit in which central power supply switches of the power shuttable-down circuits are disposed;

FIG. 4 is a plan view illustrating a planer configuration of the semiconductor integrated circuit in which power supply switches are disposed along the bottoms of the power shuttable-down circuits;

FIG. 5 is a sectional view illustrating a vertical sectional structure illustrative of SOI type MOS transistors that constitute the semiconductor integrated circuit;

FIG. 6 is a bird's eye view showing an n channel type MOS transistor having an SOI structure;

FIG. 7 is a vertical sectional view depicting the MOS transistor shown in FIG. 6;

FIG. 8 is a plan view showing the MOS transistor shown in FIG. 6;

FIG. 9 is a layout diagram illustrating a planer configuration of the power shuttable-down circuit;

FIG. 10 is a circuit diagram showing, as a comparative example of FIG. 1, circuit configurations of a power shuttable-down circuit and a power non-shutdown circuit each constituted of a bulk type MOS transistor;

FIG. 11 is a vertical sectional view showing a bulk type CMOS circuit;

FIG. 12 is a layout diagram showing, as a comparative example, a planer configuration of a power shuttable-down circuit corresponding to FIG. 10;

FIG. 13 is a diagram for describing one example illustrative of primitive cells usable by the power shuttable-down circuit and the power non-shutdown circuit;

FIG. 14 is an explanatory diagram showing one example illustrative of other primitive cells usable by the power shuttable-down circuit and the power non-shutdown circuit;

FIG. 15 is a circuit diagram illustrating a circuit in which primitive cells and the like are used in a power shuttable-down circuit and a power non-shutdown circuit;

FIG. 16 is an explanatory diagram illustrating a circuit in which primitive cells and the like are used in a power shuttable-down circuit, and layout forms thereof;

FIG. 17 is a circuit diagram typically showing a layout example of MOS transistors different in body bias form in power shuttable-down circuits and power non-shutdown circuits;

FIG. 18 is a circuit diagram illustrating a layout state in which various MOS transistors different in body bias form, conductivity type and gate oxide-film thickness are disposed adjacent to one another, and a hierarchical structure of power supply switches;

FIG. 19 is a circuit diagram showing one example of a semiconductor integrated circuit equipped with a memory circuit;

FIG. 20 is a circuit diagram illustrating a power shuttable-down circuit and a power non-shutdown circuit having a memory circuit like a static memory cell array that makes use of MOS transistors whose bodies are biased at their gates;

FIG. 21 is a circuit diagram showing an example of separate use of body biases employed in a logic circuit including sequence circuits such as flip-flops, latch circuits, etc.;

FIG. 22 is a circuit diagram showing sequence circuits and combination circuits disposed in a series configuration with a signal propagation path in a clock synchronous logic circuit;

FIG. 23 is a circuit diagram depicting another example of separate use of body biases with respect to a digital circuit and an analog circuit;

FIG. 24 is a characteristic diagram showing the relationship between a body potential of each MOS transistor and a threshold voltage thereof;

FIG. 25 is a circuit diagram illustrating, as a further example of separate use of body biases, a configuration in which power shutdown and body bias control are used in combination;

FIG. 26 is a circuit diagram showing, as a still further example of separate use of body biases, an example of body bias control for a power non-shutdown circuit;

FIG. 27 is a circuit diagram illustrating a body bias voltage control circuit;

FIG. 28 is a circuit diagram showing another example of a body bias voltage control circuit;

FIG. 29 is a circuit diagram illustrating a control form that optimizes a body potential of a subsequent-stage circuit on the basis of an output of a pre-stage circuit in a power shuttable-down circuit;

FIG. 30 is a circuit diagram illustrating a control form that optimizes a body potential of a subsequent-stage circuit on the basis of an output of a pre-stage circuit in a power non-shutdown circuit;

FIG. 31 is a circuit diagram showing one example of a body bias circuit;

FIG. 32 is a circuit diagram showing another example of a body bias circuit;

FIG. 33 is a circuit diagram showing another example of body bias control that optimizes a body potential of a subsequent-stage circuit by a pre-stage circuit;

FIG. 34 is a circuit diagram showing a further example of body bias control that optimizes a body potential of a subsequent-stage circuit by a pre-stage circuit;

FIG. 35 is a circuit diagram showing a still further example of body bias control that optimizes a body potential of a subsequent-stage circuit by a pre-stage circuit;

FIG. 36 is a circuit diagram showing an example having adopted detection circuits each of which defines a forward bias period by the number of cycles in a clock signal CK using a body bias circuit;

FIG. 37 is a circuit diagram showing a still further example of body bias control that optimizes a body potential of a subsequent-stage circuit by a pre-stage circuit;

FIG. 38 is a circuit diagram showing an example which controls each of the body bias circuits using a clock enable signal as an alternative to the detection of a change in clock signal;

FIG. 39 is a status explanatory diagram illustrating body bias states to be taken into consideration upon external power-on and power shutdown for a semiconductor integrated circuit;

FIG. 40 is a timing chart illustrating an operation timing at which a state TRS_NG occurs upon LSI power-on;

FIG. 41 is a timing chart illustrating operation timing for realizing a state TRS_OK upon LSI power-on;

FIG. 42 is a status explanatory diagram illustrating the existence of leak paths to be taken into consideration when power shutdown is performed by power supply switches in an LSI power-on state;

FIG. 43 is an explanatory diagram illustrating the states of body bias control for avoiding the formation of the leak paths of FIG. 43 when the power shutdown is performed by the power supply switches in the LSI power-on state;

FIG. 44 is a status explanatory diagram illustrating the existence of each leak path to be taken into consideration when a transition from a standby state in an LSI power-on state to an active state subsequent to an on state of each power supply switch is taken:

FIG. 45 is a timing chart illustrating operation timings provided to transition a standby state and an active state by turning on/off of each power supply switch;

FIG. 46 is a status explanatory diagram illustrating operation forms at the transition from a standby state to operation states;

FIG. 47 is a circuit diagram illustrating a circuit capable of automatically setting body biases at the shutoff of a power supply switch;

FIG. 48 is a circuit diagram illustrating a circuit that performs control on each power supply switch and control on each body bias;

FIG. 49 is a circuit diagram illustrating another circuit that performs control on each power supply switch and control on each body bias;

FIG. 50 is a plan view illustrating a device layout of each inverter that constitutes an input/output circuit;

FIG. 51 is a sectional view taken along line A-A′ of FIG. 50;

FIG. 52 is a sectional view taken along line B-B′ of FIG. 50; and

FIG. 53 is a sectional view taken along line C-C′ of FIG. 50.

Claims

1. A semiconductor integrated circuit comprising: a plurality of MOS transistors each having a source, a drain, a body, a gate insulating film provided over the body, and a gate provided over the gate insulating film, said MOS transistors being provided over an insulating thin film of a substrate;wherein the plurality of MOS transistors are provided in mixed form in such a manner that the bodies thereof are brought into floating, the voltages of the bodies are fixed and the voltages of the bodies are set variable.

2. A semiconductor integrated circuit comprising: a plurality of circuits constituted of MOS transistors each having a source, a drain, a body, a gate insulating film provided over the body, and a gate provided over the gate insulating film, said circuits being provided over an insulating thin film of a substrate; anda memory circuit included as part of the plurality of circuits,wherein the memory circuit has memory elements constituted of MOS transistors whose body voltages are fixed.

3. The semiconductor integrated circuit according to claim 2, further including: a digital circuit as part of the plurality of circuits,wherein the digital circuit has sequence circuits constituted of MOS transistors whose body voltages are fixed.

4. The semiconductor integrated circuit according to claim 3, wherein the digital circuit has combination circuits constituted of MOS transistors whose bodies are brought into floating, and the combination circuits are connected in series with the sequence circuits respectively.

5. The semiconductor integrated circuit according to claim 4, further including: another digital circuit as part of the plurality of circuits,wherein said another digital circuit has a logic circuit constituted of MOS transistors whose bodies are brought into floating.

6. A semiconductor integrated circuit comprising: a plurality of circuits constituted of MOS transistors each having a source, a drain, a body, a gate insulating film provided over the body, and a gate provided over the gate insulating film, said circuits being provided over an insulating thin film of a substrate, anda control circuit, a controlled circuit and an external interface circuit as parts of the plurality of circuits,wherein the control circuit variably controls a body potential of each MOS transistor constituting the controlled circuit according to an operation mode.

7. The semiconductor integrated circuit according to claim 6, further including: a body bias circuit, as another part of the plurality of circuits, which variably controls body potentials of MOS transistors constituting a subsequent-stage circuit on the basis of an output of a pre-stage circuit at a serial signal transmission path in the controlled circuit.

8. The semiconductor integrated circuit according to claim 6, wherein the controlled circuit has a power supply switch, and a gate oxide film of the MOS transistor constituting the power supply switch has the same thickness as a gate oxide film of each of the MOS transistors for external input/output, constituting the external interface circuit, andwherein the control circuit controls on/off of the power supply switch according to the operation mode.

9. The semiconductor integrated circuit according to claim 8, wherein the body of the MOS transistor constituting the power supply switch is connected to a source thereof.

10. The semiconductor integrated circuit according to claim 9, wherein the bodies of the MOS transistors constituting the external interface circuit are connected to sources thereof at plural spots.

11. The semiconductor integrated circuit according to claim 8, wherein in a low leak mode at shutoff of the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a reverse bias voltage at which a threshold voltage thereof becomes greater than when equal to a source voltage thereof, and in a high-speed mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a forward bias voltage at which the threshold voltage becomes smaller than when equal to the source voltage thereof.

12. The semiconductor integrated circuit according to claim 11, wherein in a low-speed mode at the supply of power by the power supply switch, the control circuit sets the body of each MOS transistor constituting the controlled circuit to the reverse bias.

13. The semiconductor integrated circuit according to claim 12, wherein in a normal mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a source voltage thereof.

14. The semiconductor integrated circuit according to claim 6, wherein when power of the semiconductor integrated circuit is turned on, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of the MOS transistor prior to or simultaneously with the application of operating power to each MOS transistor constituting the controlled circuit.

15. The semiconductor integrated circuit according to claim 14, wherein when the power of the semiconductor integrated circuit is turned off, the control circuit shuts off the bias voltage applied to hold the parasitic diode in the off state to the body of the MOS transistor simultaneously with or after the shutdown of the operating power for each MOS transistor constituting the controlled circuit.

16. The semiconductor integrated circuit according to claim 6, wherein when the power of the semiconductor integrated circuit is turned on, the control circuit connects the body of the MOS transistor to a power supply on the source side prior to or simultaneously with the application of the operating power to each MOS transistor constituting the controlled circuit.

17. The semiconductor integrated circuit according to claim 16, wherein when the power of the semiconductor integrated circuit is turned off, the control circuit shuts off the connection between the body of the MOS transistor and the power supply on the source side simultaneously with or after the shutdown of the operating power for each MOS transistor constituting the controlled circuit.

18. The semiconductor integrated circuit according to claim 8, wherein when power on a high-potential side or a low-potential side is shut down by the power supply switch, the control circuit biases the body of each MOS transistor connected to the power supply switch to a power supply lying on the side opposite to a power supply shutdown by the power supply switch, or brings the same into floating.

19. The semiconductor integrated circuit according to claim 18, wherein when the supply of power by the power supply switch is resumed, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of each MOS transistor connected to the power supply switch prior to or simultaneously with an on operation of the power supply switch.

20. The semiconductor integrated circuit according to claim 19, wherein when the supply of the power by the power supply switch is shut off, the control circuit shuts off the application of the bias voltage applied to hold the parasitic diode in the off state to the body of each MOS transistor connected to the power supply switch after or simultaneously with an off operation of the power supply switch.

21. The semiconductor integrated circuit according to claim 2, further including: a digital circuit as part of the plurality of circuits,wherein the digital circuit has sequence circuits constituted of MOS transistors whose body voltages are fixed.

22. The semiconductor integrated circuit according to claim 21, wherein the digital circuit has combination circuits constituted of MOS transistors whose bodies are brought into floating, and the combination circuits are connected in series with the sequence circuits.

23. The semiconductor integrated circuit according to claim 22, further including: another digital circuit as part of the plurality of circuits,wherein the digital circuit has a logic circuit constituted of MOS transistors whose bodies are brought into floating.

24. The semiconductor integrated circuit according to claim 23, further including: a control circuit, a controlled circuit and an external interface circuit as parts of the plurality of circuits,wherein the control circuit variably controls a body potential of a body of each MOS transistor that constitutes the controlled circuit according to an operation mode.

25. The semiconductor integrated circuit according to claim 24, further including: a body bias circuit, as another part of the plurality of circuits, which variably controls body potentials of MOS transistors constituting a subsequent-stage circuit on the basis of an output of a pre-stage circuit at a serial signal transmission path in the controlled circuit.

26. The semiconductor integrated circuit according to claim 25, wherein the controlled circuit has a power supply switch, and a gate oxide film of the MOS transistor constituting the power supply switch has the same thickness as a gate oxide film of each of the MOS transistors for external input/output, constituting the external interface circuit, andwherein the control circuit controls on/off of the power supply switch according to the operation mode.

27. The semiconductor integrated circuit according to claim 26, wherein the body of the MOS transistor constituting the power supply switch is connected to a source thereof.

28. The semiconductor integrated circuit according to claim 27, wherein the bodies of the MOS transistors constituting the external interface circuit are connected to sources thereof at plural spots.

29. The semiconductor integrated circuit according to claim 28, wherein in a low leak mode at shutoff of the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a reverse bias voltage at which a threshold voltage thereof becomes greater than when equal to a source voltage thereof, and in a high-speed mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a forward bias voltage at which the threshold voltage becomes smaller than when equal to the source voltage thereof.

30. The semiconductor integrated circuit according to claim 29, wherein in a low-speed mode at the supply of power by the power supply switch, the control circuit sets the body of each MOS transistor constituting the controlled circuit to the reverse bias.

31. The semiconductor integrated circuit according to claim 30, wherein in a normal mode at the supply of power by the power supply switch, the control circuit controls the body of each MOS transistor constituting the controlled circuit to a source voltage thereof.

32. The semiconductor integrated circuit according to claim 31, wherein upon power-on of the semiconductor integrated circuit, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of the MOS transistor prior to or simultaneously with the application of operating power to each MOS transistor constituting the controlled circuit.

33. The semiconductor integrated circuit according to claim 32, wherein upon power-off of the semiconductor integrated circuit, the control circuit shuts off the application of the bias voltage for holding the parasitic diode in the off state, which is applied to the body of the MOS transistor simultaneously with or after the shutdown of the operating power for each MOS transistor constituting the controlled circuit.

34. The semiconductor integrated circuit according to claim 33, wherein when power on a high-potential side or a low-potential side is shut down by the power supply switch, the control circuit biases the body of each MOS transistor connected to the power supply switch to a power supply lying on the side opposite to the power supply shutdown by the power supply switch, or brings the same into floating.

35. The semiconductor integrated circuit according to claim 34, wherein when the supply of power by the power supply switch is resumed, the control circuit applies a bias voltage for holding a parasitic diode in an off state to the body of each MOS transistor connected to the power supply switch prior to or simultaneously with an on operation of the power supply switch.

36. The semiconductor integrated circuit according to claim 35, further including: an analog circuit as part of the plurality of circuits,wherein the analog circuit has a circuit which allows each MOS transistor whose body voltage is fixed, to operate in a saturated region.