Claims
- 1. A method for manufacturing a semiconductor integrated circuitry including a first MISFET and a second MISFET, comprising processes of:(a) forming a gate insulating film on a main surface of a semiconductor substrate on which said first and second MISFETS are formed; (b) forming plural gate electrodes and a cap insulating film on said gate insulating film; (c) forming a low density semiconductor area for both said first and second MlSFETs, respectively, in a self-matching manner with respect to said gate electrodes; (d) forming first side wall spacers on side surfaces of said gate electrodes; (e) forming second side wall spacers outside said first side wall spacers; (f) forming a high density semiconductor area in a self-matching manner with respect to said second side wall spacers of said second MISFET; (g) depositing an Interlaminar insulating film comprised of a silicon oxide film over said semiconductor substrate; (h) etching said interlaminar insulating film and said second side wall spacers in a self-matching manner with respect to said first side wall spacers of said first MISFET to open connecting holes; and (i) forming a conductor in each of said connecting holes.
- 2. A method for manufacturing a semiconductor integrated circuitry including a first MISFET and a second MISFET, comprising processes of:(a) forming a gate insulating film on a main surface of a semiconductor substrate on which said first and second MISFETS are formed; (b) forming plural gate electrodes and a cap insulating film on said gate insulating film; (c) forming a low density semiconductor area for both said first and second MISFETs, respectively; (d) depositing a silicon nitride film over said semiconductor substrate including side surfaces of said gate electrodes; (e) forming side wall spacers on side surfaces of said gate electrodes with said silicon nitride film therebetween; (f) forming a high density semiconductor area in a self-matching manner with respect to said side wall spacers of said second MISFET; (g) depositing an interlaminar insulating film comprised of a silicon oxide film over said semiconductor substrate; (h) etching said interlaminar insulating film and said side wall spacers in a self-matching manner with respect to said silicon nitride film to form openings, and further etching said silicon nitride film at the bottom of each of said openings to open connecting holes; and (i) forming a conductor in each of said connecting holes.
- 3. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 1, wherein in said process (c), phosphorus is implanted in the semiconductor area of said first MISFET and at least in one or more low density semiconductor areas of said second MISFET is implanted with arsenic.
- 4. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 1, whereinin said process (a), the gate insulating films are formed for both said first MISFET and said second MISFET in the same process.
- 5. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 1, whereinsaid process (a) for forming said gate insulating film includes: a process for forming a first gate insulating film in an area where said first and second MISFETs are formed; a process for removing said first gate insulating film selectively from the area where said second MISFET is formed; and a process for forming a second gate insulating film in an area where said second MISFET is formed.
- 6. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 1, whereinsaid gate insulating film is a tunnel insulating film of a floating gate type MISFET comprising a nonvolatile memory and said process for forming said gate insulating film includes; a process for forming floating gate electrodes of said floating gate type MISFET; and a process for forming control electrodes of said floating gate type MISFET on said floating gate electrodes via an insulating film.
- 7. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 6, whereinprior to said process (a) a process is provided for forming a tunnel insulating film of a floating gate type MISFET comprising a nonvolatile memory on the main surface of said semiconductor substrate and forming floating gate electrodes of said floating gate type MISFET on said tunnel insulating film.
- 8. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 7, whereingate electrodes formed in said process (b) are formed in the same process as a process for forming control gate electrodes of said floating gate type MISFET.
- 9. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 7, whereinsaid tunnel insulating film is formed thicker than said gate insulating film formed in said process (a).
- 10. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 1, whereinprior to said process (g), a process is provided for depositing a second silicon nitride film in an area where said second MISFET is formed, etching said interlaminar insulating film in an area where a conductor portion connecting said second MISFET to a member formed in the upper layer of said second MISFET is formed on conditions decided to take an etching selection ratio for said second silicon nitride film to form openings, further etching the second silicon nitride film at the bottom of each of said openings to open connecting holes, and forming said conductor portion.
- 11. A method for manufacturing a semiconductor integrated circuitry, as defined in claim 10, whereinsaid second silicon nitride film is formed in the same process as that of a silicon nitride film formed as said first insulating film.
Priority Claims (2)
Number |
Date |
Country |
Kind |
9-092607 |
Apr 1997 |
JP |
|
9-092608 |
Apr 1997 |
JP |
|
Parent Case Info
This is a divisional of application Ser. No. 09/381,345, filed Sep. 20, 1999, now U.S. Pat. No. 6,503,794 the entire disclosure of which is hereby incorporated by reference.
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