Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.
A semiconductor memory device that has a three-dimensional structure in which memory cells are arranged three-dimensionally has been proposed. When manufacturing such a semiconductor memory device, a stacked body that includes multiple conductive layers is formed on a substrate. Then, holes that pierce the stacked body are formed. When increasing the number of stacks of the stacked body, it becomes difficult to form the holes by collective patterning. It is desirable to be able to increase the number of stacks and increase the memory capacity per surface area.
A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The first stacked body includes a plurality of first conductive layers arranged in a first direction. The second stacked body is arranged in the first direction with the first stacked body and includes a plurality of second conductive layers arranged in the first direction. The intermediate conductive layer provides between the first stacked body and the second stacked body. The intermediate insulating layer provides between the intermediate conductive layer and the second stacked body. The semiconductor pillar includes a first part, a second part, and a third part. The first part extends in the first direction through the first stacked body and through the intermediate conductive layer. The second part extends in the first direction through the second stacked body. The third part is provided inside the intermediate insulating layer and is continuous with the first part and the second part. A central axis of the first part is shifted from a central axis of the second part in a second direction intersecting the first direction. The charge storage film includes a first charge storage portion and a second charge storage portion. The first charge storage portion is provided between the first stacked body and the first part. The second charge storage portion is provided between the second stacked body and the second part and between the intermediate insulating layer and the third part. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.
As shown in
The first stacked body ML1 is provided on a major surface BSm of the base body BS. The second stacked body ML2 is provided on the first stacked body ML1. The intermediate conductive layer 31 is provided between the first stacked body ML1 and the second stacked body ML2. The intermediate insulating layer 32 is provided between the intermediate conductive layer 31 and the second stacked body ML2.
A direction from the first stacked body ML1 toward the second stacked body ML2 is taken as a Z-direction. The major surface BSm intersects the Z-direction. One direction perpendicular to the Z-direction is taken as an X-direction. A direction perpendicular to the Z-direction and the X-direction is taken as a Y-direction.
The semiconductor pillar 50 includes a first part P1 extending in the Z-direction through the first stacked body ML1 and through the intermediate conductive layer 31, a second part P2 extending in the Z-direction through the second stacked body ML2 at a different position from the first part P1, and a third part P3 that is provided inside the intermediate insulating layer 32 and is continuous with the first part P1 and the second part P2. For example, a central axis of the first part P1 is shifted from a central axis of the second part P2 in a direction (for example, X-direction or Y-direction) crossing the Z-direction.
The memory film 40 includes, for example, a blocking insulating film 41, a charge storage film 42, and a tunneling insulating film 43. The memory film 40 is provided between the first part P1 and the first stacked body ML1, between the third part P3 and the intermediate insulating layer 32, and between the second part P2 and the second stacked body ML2. The memory film 40 is discontinuous between the first part P1 and the intermediate conductive layer 31. For example, the memory film 40 is not provided between the first part P1 and the intermediate conductive layer 31.
The charge storage film 42 includes a first charge storage portion 42a and a second charge storage portion 42b. The first charge storage portion 42a is provided between the first part P1 and the first stacked body ML1. The second charge storage portion 42b is provided between the second part P2 and the second stacked body ML2. The second charge storage portion 42b is provided also between the third part P3 and the intermediate insulating layer 32.
As shown in
The blocking insulating film 41 is provided between the first charge storage portion 42a and the first stacked body ML1, between the second charge storage portion 42b and the intermediate insulating layer 32, and between the second charge storage portion 42b and the second stacked body ML2.
The tunneling insulating film 43 is provided between the first part P1 and the first charge storage portion 42a, between the third part P3 and the second charge storage portion 42b, and between the second part P2 and the second charge storage portion 42b.
The insulating film 61 is provided in at least a portion between the first part P1 and the intermediate conductive layer 31. The semiconductor pillar 50 is insulated from the intermediate conductive layer 31 by the insulating film 61.
The semiconductor pillar 50 includes, for example, a semiconductor film 51. The semiconductor pillar 50 may include a core insulating film 52 in addition to the semiconductor film 51. The core insulating film 52 extends in the Z-direction through the first stacked body ML1, through the intermediate conductive layer 31, through the intermediate insulating layer 32, and through the second stacked body ML2. The semiconductor film 51 is provided between the core insulating film 52 and the memory film 40 and between the core insulating film 52 and the insulating film 61. For example, a thickness t1 of the semiconductor film 51 between the core insulating film 52 and the memory film 40 is thinner than a thickness t2 of the semiconductor film 51 between the core insulating film 52 and the insulating film 61. For example, the thickness t1 and the thickness t2 are lengths in one direction perpendicular to the Z-direction.
The charge storage film 42 includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film 61 includes, for example, silicon oxide. The concentration of the first element of the insulating film 61 is lower than the concentration of the first element of the charge storage film 42. The insulating film 61 may not include the first element. At least a portion of the insulating film 61 does not overlap the charge storage film 42 in a direction (e.g., the X-direction) intersecting the Z-direction.
In other words, in the embodiment, the memory film 40 that includes the charge storage film 42 is not provided between the intermediate conductive layer 31 and the first part P1.
On the other hand, there is a reference example in which the memory film 40 that includes the charge storage film 42 is provided also between the intermediate conductive layer 31 and the first part P1. In the reference example, for example, if the intermediate conductive layer 31 includes a stepped portion 31s as shown in
Conversely, in the embodiment, there is no memory film 40 including the charge storage film 42 between the first part P1 and the intermediate conductive layer 31 including the stepped portion 31s. Thereby, the fluctuation of the threshold voltage is reduced even in the case where the intermediate conductive layer 31 includes the stepped portion 31s.
In the embodiment, the insulating film 61 is provided between the intermediate conductive layer 31 and the first part P1 instead of the memory film 40 including the charge storage film 42 recited above. The first part P1 (the semiconductor film 51) and the intermediate conductive layer 31 are electrically insulated by the insulating film 61.
As described below, for example, the first part P1 and the second part P2 recited above are formed by forming holes in each of the first stacked body ML1 and the second stacked body ML2 and forming the semiconductor film 51 inside these holes. By the positions of these two holes being shifted, the positions of the first part P1 and the second part P2 are shifted; and the stepped portion 31s occurs. In the embodiment, at least a portion of the insulating film 61 does not overlap the charge storage film 42 in a direction (e.g., the X-direction) intersecting the Z-direction. In other words, there is no memory film 40 including the charge storage film 42 between the first part P1 and the intermediate conductive layer 31. Thereby, the fluctuation of the threshold voltage is reduced even if the stepped portion 31s occurs. In the embodiment, for example, even if the number of stacks increases, good characteristics can be maintained. For example, to easily increase the number of stacks; and the memory capacity per surface area can be increased.
In the example, the first stacked body ML1 includes multiple first conductive layers 11 arranged in the Z-direction . In the example, the first stacked body ML1 includes the multiple first conductive layers 11 and multiple first insulating layers 12 arranged alternately along the Z-direction.
The second stacked body ML2 includes multiple second conductive layers 21 arranged in the Z-direction. In the example, the second stacked body ML2 includes the multiple second conductive layers 21 and multiple second insulating layers 22 arranged alternately in the Z-direction.
The third part P3 is wider than each of the first part P1 and the second part P2. In other words, the length of the third part P3 in at least one direction (e.g., at least one of a X-direction or a Y-direction) intersecting the Z-direction is longer than each of the length of the first part P1 in the one direction (e.g., the at least one of the X-direction or the Y-direction) recited above intersecting the Z-direction and the length of the second part P2 in the one direction (e.g., the at least one of the X-direction or the Y-direction) recited above intersecting the Z-direction.
There is a reference example in which the first part P1 and the second part P2 are connected without providing the third part P3. A connection unit between the first part P1 and the second part P2 is positioned inside the intermediate insulating layer 32. In the reference example, the semiconductor film 51 is bent at a portion distal to the intermediate conductive layer 31 and the second conductive layer 21. In the case where the semiconductor film 51 is bent at the portion distal to the intermediate conductive layer 31 and the second conductive layer 21, the resistance of the semiconductor film 51 increases. For example, the ON current decreases due to the increase of the resistance of the semiconductor film 51.
In the embodiment, the third part P3 is provided between the first part P1 and the second part P2. The third part P3 is wider than each of the first part P1 and the second part P2. The first part P1 and the second part P2 are connected smoothly by the third part P3. The bend of the semiconductor film 51 at the portion distal to the intermediate conductive layer 31 and the second conductive layer 21 is suppressed by the third part P3. For example, the increase of the resistance of the semiconductor film 51 is suppressed. Thereby, a good ON current can be maintained.
In the embodiment, even in the case where the positions of the first part P1 and the second part P2 are shifted and the stepped portion 31s occurs, the bend of the semiconductor film 51 at the portion distal to the intermediate conductive layer 31 and the second conductive layer 21 is suppressed; and a good ON current can be maintained. Thereby, a good ON current can be maintained even in the case where the number of stacks in the stacked body is increased and the positions of the multiple holes are shifted. In the embodiment, for example, even if the number of stacks is increased, good characteristics can be maintained. For example, to easily increase the number of stacks; and the memory capacity per surface area can be increased.
In the embodiment, there is a region where there is no memory film 40 in a portion between the intermediate conductive layer 31 and the first part P1. The insulating film 61 is provided in this region.
In the semiconductor memory device 120 according to the embodiment as shown in
As shown in
In the embodiment, the third part P3 is provided between the first part P1 and the second part P2. The first part P1 and the second part P2 are connected smoothly by the third part P3. Thereby, a good ON current can be maintained. In the embodiment, for example, even if the number of stacks is increased, good characteristics can be maintained. For example, to easily increase the number of stacks; and the memory capacity per surface area can be increased.
In the embodiment, there is a region where there is no memory film 40 or semiconductor film 51 in a portion between the intermediate conductive layer 31 and the core insulating film 52. The insulating film 61 is provided in this region.
In the semiconductor memory device 130 according to the embodiment as shown in
The insulating film 61 may be formed as one body with the core insulating film 52. In other words, a boundary may not exist between the insulating film 61 and the core insulating film 52.
In the embodiment, the third part P3 is provided between the first part P1 and the second part P2. The first part P1 and the second part P2 are connected smoothly by the third part P3. Thereby, a good ON current is obtained. In the embodiment, for example, even if the number of stacks is increased, good characteristics can be maintained. For example, to easily increase the number of stacks; and the memory capacity per surface area can be increased.
A method for manufacturing a semiconductor memory device according to the embodiment corresponds to the method for manufacturing the semiconductor memory device 110.
As shown in
An intermediate film 31f is formed on the first structure body MLf1. An intermediate insulating film 32f is formed on the intermediate film 31f. The intermediate film 31f is formed using a material different from the first film 11f and the second film 12f. For example, the intermediate film 31f is formed using at least one of aluminum oxide or hafnium oxide.
As shown in
As shown in
As shown in
Thereby, the first hole MH1 that includes a first region MHr1 and a second region MHr2 is formed, where the first region MHr1 extends along the Z-direction through the first structure body MLf1 and through the intermediate film 31f, and the second region MHr2 is continuous with the first region MHr1 and extends along the Z-direction through the intermediate insulating film 32f. The diameter of the second region MHr2 is larger than the diameter of the first region MHr1.
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
The intermediate film 31f is removed as shown in
As shown in
The first films 11f and the third films 21f are removed as shown in
As shown in
A conductive material is provided inside the first space SP1, inside the second spaces SP2, and inside the third spaces SP3. Thereby, as shown in
By implementing the processes recited above, the semiconductor memory device 110 can be manufactured.
In the embodiment, the formation of the hole piercing the structure body is performed by dividing into two formations. In other words, the intermediate film 31f, the intermediate insulating film 32f, and the second structure body MLf2 are formed on the first structure body MLf1 after forming the first hole MH1 in the first structure body MLf1. Subsequently, the second hole MH2 is formed. Thereby, a hole can be formed that is deeper than the depth of a hole that can be formed as a whole in the structure body.
In the case where the formation of the hole is performed by dividing into two formations, a portion of the memory film formed inside the hole may be removed. In the embodiment, the insulating film 61 is formed by oxidizing the semiconductor film 51 exposed from the memory film 40. Thereby, shorts between the semiconductor pillar 50 (the semiconductor film 51) and the conductive layers (e.g., the intermediate conductive layer 31, etc.) can be suppressed. The yield of the manufacturing processes of the semiconductor memory device increases.
The embodiment corresponds to a method for manufacturing the semiconductor memory device 120 according to the second embodiment described above.
Similarly to the manufacturing method according to the fourth embodiment described above, the processes shown in
As shown in
A conductive material is provided inside the first space SP1, inside the second spaces SP2, and inside the third spaces SP3.
Thereby, as shown in
By implementing the processes recited above, the semiconductor memory device 120 can be manufactured.
In the embodiment, the process of removing the memory film 40 exposed inside the first space SP1 is omitted. Thereby, the number of processes can be reduced.
The embodiment corresponds to a method for manufacturing the semiconductor memory device 130 according to the third embodiment described above.
Similarly to the manufacturing method according to the fourth embodiment described above, the processes shown in
As shown in
The first films 11f and the third films 21f are removed as shown in
A conductive material is provided inside the first space SP1, inside the second spaces SP2, and inside the third spaces SP3. Thereby, as shown in
By implementing the processes recited above, the semiconductor memory device 130 can be manufactured.
In the embodiment, the process of removing the memory film 40 exposed inside the first space SP1 is omitted. Thereby, the number of processes can be reduced.
The embodiment corresponds to a method for manufacturing the semiconductor memory device 130 according to the third embodiment. The embodiment is a manufacturing method in the case where the intermediate film 31f is not formed between the first structure body MLf1 and the intermediate insulating film 32f.
As shown in
As shown in
As shown in
The second hole MH2 that extends in the Z-direction through the second structure body MLf2 is formed at a different position from the first hole MH1. The second hole MH2 is continuous with the first hole MH1. The first member 71 and the second member 72 are removed as shown in
As shown in
As shown in
As shown in
As shown in
The first films 11f and the second films are removed as shown in
The portion of the semiconductor film 51 exposed from the memory film 40 is oxidized via the second spaces SP2. The oxidized portion of the semiconductor film 51 is used as the insulating film 61.
The insulating film 61 may be formed on the inner wall of the first space SP1, the inner wall of the second space SP2 and the inner wall of the third space SP3. In this case, a film including silicon oxide is formed on the inner wall of the first space SP1, the inner wall of the second space SP2 and the inner wall of the third space SP3. Thereby, the insulating film 61 is formed.
Subsequently, conductive layers (the first conductive layers 11, the intermediate conductive layer 31, and the second conductive layers 21) are formed inside the second spaces SP2 and inside the third spaces SP3. Thereby, the semiconductor memory device 130 shown in
In the embodiment, the insulating film 61 can be formed by omitting the formation of the intermediate film 31f and the removal of the intermediate film 31f. Thereby, the number of manufacturing processes can be reduced.
According to the embodiments described above, for example, a semiconductor memory device and a method for manufacturing the semiconductor memory device can be realized in which the memory capacity per surface area can be increased.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
This application is a continuation of U.S. application Ser. No. 16/511,111, filed Jul. 15, 2019, which is a continuation of U.S. application Ser. No. 15/863,490, filed Jan. 5, 2018 (now U.S. Pat. No. 10,431,590), which is a continuation of U.S. application Ser. No. 15/264,903, filed Sep. 14, 2016 (now U.S. Pat. No. 9,985,044), which is based upon and claims the benefit of priority from U.S. Provisional Patent Application 62/306,672, filed on Mar. 11, 2016; the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
62306672 | Mar 2016 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 16511111 | Jul 2019 | US |
Child | 16793359 | US | |
Parent | 15863490 | Jan 2018 | US |
Child | 16511111 | US | |
Parent | 15264903 | Sep 2016 | US |
Child | 15863490 | US |