Semiconductor memory device and method of manufacturing the same

Abstract

A polysilicon film forming a memory gate interconnection and the like includes a part extending from a part positioned on one side surface of a control gate interconnection to a side opposite to a side where the control gate interconnection is positioned, and that part serves as a pad portion. A contact hole is formed to expose the pad portion. The height of a part of the polysilicon film that is positioned on one side surface of the control gate interconnection is set equal to or lower than the height of the control gate interconnection so that the polysilicon film forming a memory gate interconnection and the like does not two-dimensionally overlap the control gate interconnection. Therefore, a semiconductor memory device with increased process margin can be obtained.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial plan view of a nonvolatile semiconductor memory device in accordance with a first embodiment of the present invention.

FIG. 2 is a cross sectional view taken along line II-II shown in FIG. 1 in the first embodiment.

FIG. 3 is a cross sectional view taken along line III-III shown in FIG. 1 in the first embodiment.

FIG. 4 shows a circuit of a memory cell in the first embodiment.

FIG. 5 is a schematic cross sectional view of a memory cell to illustrate an operation of the nonvolatile semiconductor memory device in the first embodiment.

FIG. 6 shows an example of a voltage applied to each part of a memory cell to illustrate an operation of the nonvolatile semiconductor memory device in the first embodiment.

FIG. 7 is a cross sectional view showing a step of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 1-FIG. 3 in the first embodiment.

FIG. 8 is a cross sectional view showing a step performed after the step shown in FIG. 7 in the first embodiment.

FIG. 9 is a cross sectional view showing a step performed after the step shown in FIG. 8 in the first embodiment.

FIG. 10 is a partial plan view showing a step performed after the step shown in FIG. 9 in the first embodiment.

FIG. 11 is a cross sectional view taken along line XI-XI shown in FIG. 10 in the first embodiment.

FIG. 12 is a cross sectional view showing a step performed after the step shown in FIG. 11 in the first embodiment.

FIG. 13 is a cross sectional view showing a step performed after the step shown in FIG. 12 in the first embodiment.

FIG. 14 is a cross sectional view showing a step performed after the step shown in FIG. 13 in the first embodiment.

FIG. 15 is a cross sectional view showing a step performed after the step shown in FIG. 14 in the first embodiment.

FIG. 16 is a cross sectional view showing a step performed after the step shown in FIG. 15 in the first embodiment.

FIG. 17 is a cross sectional view showing a step performed after the step shown in FIG. 16 in the first embodiment.

FIG. 18 is a cross sectional view showing a step performed after the step shown in FIG. 17 in the first embodiment.

FIG. 19 is a cross sectional view showing a step performed after the step shown in FIG. 18 in the first embodiment.

FIG. 20 is a cross sectional view showing a step performed after the step shown in FIG. 19 in the first embodiment.

FIG. 21 is a cross sectional view showing a step performed after the step shown in FIG. 20 in the first embodiment.

FIG. 22 is a cross sectional view showing a step performed after the step shown in FIG. 21 in the first embodiment.

FIG. 23 is a cross sectional view showing a step performed after the step shown in FIG. 22 in the first embodiment.

FIG. 24 is a cross sectional view showing a step performed after the step shown in FIG. 23 in the first embodiment.

FIG. 25 is a partial plan view of a nonvolatile semiconductor memory device in accordance with a second embodiment of the present invention.

FIG. 26 is a cross sectional view taken along line XXVI-XXVI shown in FIG. 25 in the second embodiment.

FIG. 27 is a cross sectional view taken along line XXVII-XXVII shown in FIG. 25 in the second embodiment.

FIG. 28 is a cross sectional view showing a step of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 25-FIG. 27 in the second embodiment.

FIG. 29 is a cross sectional view showing a step performed after the step shown in FIG. 28 in the second embodiment.

FIG. 30 is a cross sectional view showing a step performed after the step shown in FIG. 29 in the second embodiment.

FIG. 31 is a partial plan view showing a step performed after the step shown in FIG. 30 in the second embodiment.

FIG. 32 is a cross sectional view taken along line XXXII-XXXII shown in FIG. 31 in the second embodiment.

FIG. 33 is a cross sectional view showing a step performed after the step shown in FIG. 32 in the second embodiment.

FIG. 34 is a cross sectional view showing a step performed after the step shown in FIG. 33 in the second embodiment.

FIG. 35 is a cross sectional view showing a step performed after the step shown in FIG. 34 in the second embodiment.

FIG. 36 is a cross sectional view showing a step performed after the step shown in FIG. 35 in the second embodiment.

FIG. 37 is a cross sectional view showing a step performed after the step shown in FIG. 36 in the second embodiment.

FIG. 38 is a cross sectional view showing a step performed after the step shown in FIG. 37 in the second embodiment.

FIG. 39 is a cross sectional view showing a step performed after the step shown in FIG. 38 in the second embodiment.

FIG. 40 is a cross sectional view showing a step performed after the step shown in FIG. 39 in the second embodiment.

FIG. 41 is a cross sectional view showing a step performed after the step shown in FIG. 40 in the second embodiment.

FIG. 42 is a cross sectional view showing a step performed after the step shown in FIG. 41 in the second embodiment.

FIG. 43 is a partial plan view of a nonvolatile semiconductor memory device in accordance with a third embodiment of the present invention.

FIG. 44 is a cross sectional view taken along line XLIV-XLIV shown in FIG. 43 in the third embodiment.

FIG. 45 is a cross sectional view taken along line XLV-XLV shown in FIG. 43 in the third embodiment.

FIG. 46 is a cross sectional view showing a step of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 43-FIG. 45 in the third embodiment.

FIG. 47 is a cross sectional view showing a step performed after the step shown in FIG. 46 in the third embodiment.

FIG. 48 is a partial plan view showing a step performed after the step shown in FIG. 47 in the third embodiment.

FIG. 49 is a cross sectional view taken along line XLIX-XLIX shown in FIG. 48 in the third embodiment.

FIG. 50 is a cross sectional view showing a step performed after the step shown in FIG. 49 in the third embodiment.

FIG. 51 is a cross sectional view showing a step performed after the step shown in FIG. 50 in the third embodiment.

FIG. 52 is a partial plan view of a nonvolatile semiconductor memory device in accordance with a fourth embodiment of the present invention.

FIG. 53 is a cross sectional view taken along line LIII-LIII shown in FIG. 52 in the fourth embodiment.

FIG. 54 is a cross sectional view taken along line LIV-LIV shown in FIG. 52 in the fourth embodiment.

FIG. 55 is a cross sectional view showing a step of a method of manufacturing the nonvolatile semiconductor memory device shown in FIG. 52-FIG. 54 in the fourth embodiment.

FIG. 56 is a cross sectional view showing a step performed after the step shown in FIG. 55 in the fourth embodiment.

FIG. 57 is a partial plan view showing a step performed after the step shown in FIG. 56 in the fourth embodiment.

FIG. 58 is a cross sectional view taken along line LVIII-LVIII shown in FIG. 57 in the fourth embodiment.

FIG. 59 is a cross sectional view showing a step performed after the step shown in FIG. 58 in the fourth embodiment.

FIG. 60 is a cross sectional view showing a step performed after the step shown in FIG. 59 in the fourth embodiment.

Claims

1. A semiconductor memory device comprising: a first conductor portion formed on a surface of a semiconductor substrate to have a prescribed height and opposite side surfaces and extend in a first direction;a second conductor portion formed on one side surface of said opposite side surfaces of said first conductor portion to be electrically separated from said first conductor portion and not to exceed said height of said first conductor portion;an interlayer insulating film formed on said semiconductor substrate to cover said first conductor portion and said second conductor portion;a contact member formed to pass through said interlayer insulating film; anda first protrusion portion formed in said second conductor portion to extend from a part positioned on said one side surface of said first conductor portion to a side opposite to a side where said first conductor potion is positioned and to be in contact with said contact member so that a prescribed voltage is applied to said second conductor portion.

2. A semiconductor memory device comprising: a first conductor portion formed on a surface of a semiconductor substrate to have a prescribed height and opposite side surfaces and extend in a first direction;a second conductor portion formed on one side surface of said opposite side surfaces of said first conductor portion to be electrically separated from said first conductor portion;an interlayer insulating film formed on said semiconductor substrate to cover said first conductor portion and said second conductor portion; anda contact member formed to pass through said interlayer insulating film, whereinsaid second conductor portion includes a first protrusion portion extending from a part positioned on said one side surface of said first conductor portion to a side opposite to a side where said first conductor portion is positioned and being in contact with said contact member so that a prescribed voltage is applied to said second conductor portion, anda height of a part of said second conductor portion that is positioned on said one side surface is set to be at most said height of said first conductor portion such that said second conductor portion does not two-dimensionally overlap said first conductor portion.

3. The semiconductor memory device according to claim 2, wherein said second conductor portion includes a pair of opposing portions formed to be spaced apart from and opposed to each other, andsaid first protrusion portion is formed in a region sandwiched between said pair of opposing portions.

4. The semiconductor memory device according to claim 3, wherein said second conductor portion includes, as said pair of opposing portions,a second protrusion portion extending to a side opposite to a side where said first conductor portion is positioned anda third protrusion portion extending to a side opposite to a side where said first conductor portion is positioned and being opposed to said second protrusion portion at a distance in said first direction.

5. The semiconductor memory device according to claim 3, wherein a plurality of said first conductor portions and a plurality of said second conductor portions are formed, andone second conductor portion and the other second conductor portion of a plurality of said second conductor portions are formed as said pair of opposing portions to be spaced apart from each other in a second direction orthogonal to said first direction.

6. The semiconductor memory device according to claim 3, wherein a plurality of said first conductor portions and a plurality of said second conductor portions are formed, andone second conductor portion and the other second conductor portion of a plurality of said second conductor portions are formed such that an end portion of said one second conductor portion and an end portion of said other second conductor portion are formed as said pair of opposing portions to be spaced apart from each other in said first direction.

7. The semiconductor memory device according to claim 2, wherein said first conductor portion includesa first gate electrode formed on said semiconductor substrate with a first gate insulating film interposed anda first interconnection electrically connected to said first gate electrode,said second conductor portion includesa second gate electrode formed on said semiconductor substrate with a second gate insulating film interposed and on one side surface of said first gate electrode with a first insulating film interposed anda second interconnection electrically connected to said second gate electrode, andsaid semiconductor memory device further comprises:a first impurity region of a prescribed conductivity type formed in a region of said semiconductor substrate that is positioned on a side opposite to a side where said second gate electrode is positioned with respect to said first gate electrode; anda second impurity region of said prescribed conductivity type formed in a region of said semiconductor substrate that is positioned on a side opposite to a side where said first gate electrode is positioned with respect to said second gate electrode.

8. A method of manufacturing a semiconductor memory device comprising the steps of: forming on a main surface of a semiconductor substrate a first conductor portion having a prescribed height and opposite side surfaces and extending in a first direction;forming a conductive layer on a surface of said semiconductor substrate with a first insulating film interposed to cover said first conductor portion;forming a resist pattern on said conductive layer by performing a photolithography process using a prescribed mask;forming a voltage application portion for applying a prescribed voltage by performing processing on said conductive layer using said resist pattern as a mask;leaving a part of said conductive layer that is positioned on a side of one side surface of said first conductor portion and removing a part of said conductive layer positioned in the other part thereby forming a second conductor portion including said voltage application portion on said one side surface of said first conductor portion with said first insulating film interposed;forming an interlayer insulating film to cover said first conductor portion and said second conductor portion; andforming an opening portion in said interlayer insulating film to expose said voltage application portion in said second conductor portion, and forming a contact member in said opening portion to be electrically connected to said voltage application portion, whereinin said step of forming a resist pattern, an exposure process is performed on a resist coated on said semiconductor substrate such that the resist is left after development as a result of poor resolution, from the resist pattern left after development based on said prescribed mask to a part of said conductive layer that covers said one side surface of said first conductor portion, whereby a resist pattern is formed as said resist pattern including a resist pattern formed based on said prescribed mask as a first resist pattern and a resist left as a result of poor resolution as a second resist pattern.

9. The method of manufacturing a semiconductor memory device according to claim 8, wherein said step of forming a first conductor portion includes the step of forming a pair of a first portion and a second portion spaced apart in said first direction, each extending in a second direction orthogonal to said first direction, andin said step of forming a resist pattern, said resist pattern is formed to cover a part of said conductive layer that is positioned between a part of said conductive layer that covers said first portion and a part of said conductive layer that covers said second portion.

10. The method of manufacturing a semiconductor memory device according to claim 8, wherein said step of forming a first conductor portion includes the steps offorming a first gate electrode on said semiconductor substrate with a first gate insulating film interposed andforming a first interconnection electrically connected to said first gate electrode,said step of forming a second conductor portion includes the steps offorming a second gate electrode on said semiconductor substrate with a second gate insulating film interposed and on one side surface of said first gate electrode with a first insulating film interposed andforming a second interconnection electrically connected to said second gate electrode, andsaid method further comprises the step of forming a first impurity region of a prescribed conductivity type in a region of said semiconductor substrate that is positioned on a side opposite to a side where said second gate electrode is positioned with respect to said first gate electrode, and forming a second impurity region of said prescribed conductivity type in a region of said semiconductor substrate that is positioned on a side opposite to a side where said first gate electrode is positioned with respect to said second gate electrode.