Semiconductor memory device and method of outputting data strobe signal thereof

Abstract

A semiconductor memory device is disclosed. The device comprises at least one data input/output reference signal input and output pin and a plurality of integrated circuits, each with a data input/output reference signal input and output pad connected to the data input/output reference signal input and output pin. Each integrated circuit further comprises a data input/output reference signal input and output buffer for buffering a data input/output reference signal input from the data input/output reference signal input and output pad when data is input. This buffer also buffers an internally generated data input/output reference signal, and outputs the buffered signal when data is output. The internally generated data input/output reference signal output can be disabled on each integrated circuit in response to a control signal, thus allowing a single one of the plurality of integrated circuits to be selected to generate the reference signal.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device and more particularly to the semiconductor memory device comprising at least two integrated circuits in which data is input and output in association with a reference (called a data strobe signal) and a method for outputting the data strobe signal out of the semiconductor memory device.

[0003] 2. Description of Related Art

[0004] Generally, a double data rate (DDR) synchronous semiconductor memory device uses a data strobe signal as a reference signal to capture input data and output data. Accordingly, the data strobe signal is required to be generated in time for capturing the data.

[0005] In conventional semiconductor memory devices, one data strobe signal is generated for inputting and outputting four bits or eight bits of data with one clock cycle to and from the semiconductor memory device, so that the conventional semiconductor memory device has one data strobe signal pin.

[0006] Sometimes, the semiconductor memory device is formed by packaging two or more DDR synchronous semiconductor memory devices together. Each DDR synchronous semiconductor memory device is referred to hereinafter as an integrated circuit in the same package as a data strobe signal pad.

[0007] FIG. 1 illustrates a block diagram of a conventional semiconductor memory device 100 comprising first and second integrated circuits 110-1 and 110-2. The first and second integrated circuits include data strobe signal pads 12-1 and 12-2, data input and output pads 14-1 and 14-2, data strobe signal input and output buffers (DQSBs) 116-1 and 116-2, and data input and output buffers (DIOBs) 18-1 and 18-2, respectively.

[0008] The semiconductor memory device includes a data strobe signal (DQS) pin 11, which is commonly connected to the data strobe signal pads 12-1 and 12-2 formed in the first and second integrated circuits 110-1 and 110-2, respectively. The semiconductor memory device further includes a plurality of data input and output (DQ) pins 13-1 and 13-2, connected to respective data input and output pads 14-1 and 14-2 in the integrated circuits 110-1 and 110-2.

[0009] For write operations, the data input and output buffers 18-1 and 18-2 generate input data DI to be written into the integrated circuits 110-1 or 110-2 by buffering data DQ that is externally input respectively through the data input and output pins 13-1 and 13-2. For read operations, the data input and output buffers 18-1 and 18-2 generate the data DQ by buffering output data DO read respectively from the integrated circuits 110- 1 and 110-2.

[0010] For write operations, the data strobe signal input/output buffers 116-1 and 116-2 each receive and buffer the data strobe signal DQS externally input through the external data strobe signal input and output pin 11 to generate input data strobe signal DSI for respective integrated circuits 110-1 and 110-2. For read operations, buffers 116-1 and 116-2 each receive and buffer output data strobe signal DSO internally generated to generate the data strobe signal DQS.

[0011] The input data strobe signals DSI generated by the data strobe signal input/output buffers 116-1 and 116-2 are input to the data input/output buffers 18-1 and 18-2 in the integrated circuits 110-1, 110-2, respectively. Each data strobe signal DSI is used as a reference signal for capturing the input data DI. In the same manner, the output data strobe signal DSO is used as a reference signal for capturing the output data DO.

[0012] Data input and output operation of the semiconductor memory device shown in FIG. 1 will be described below.

[0013] For inputting four-bit or eight-bit data to the semiconductor memory device 100, the data strobe signal DQS is input through the data strobe signal input pin 11 and at the same time four bits or eight bits of data DQ are input to the semiconductor memory device via the data input/output pins 13-1 and 13-2. Then, the data strobe signal input/output buffers 116-1 and 116-2 buffer the data strobe signal DQS, thereby generating the input data strobe signal DSI. The data input and output buffers 18-1 and 18-2 buffer the data DQ to be input to the semiconductor memory device, thereby generating the input data DI.

[0014] For outputting four bits or eight bits of data DQ from the semiconductor memory device, a data strobe signal DQS is required to be output from the semiconductor memory device. Thus, the data strobe signal input/output buffers 116-1 and 116-2 in the integrated circuits 110-1 and 110-2 buffer, respectively, the output data strobe signals DSO, which are internally generated, thereby generating the data strobe signals DQS to be output from the semiconductor memory device through the data strobe signal input/output pin 11. At the same time, the data input/output buffers 18-1 and 18-2 buffer the output data DO read from the integrated circuits 10-1 and 10-2, thereby generating the data DQ to be output through the data input and output pins 13-1 and 13-2.

[0015] Typically, the length of the signal line between the data strobe signal pad 12-1 in the integrated circuit 110-1 and the data strobe signal pin 11 is different from that between the data strobe signal pad 12-2 in the integrated circuit 110-2 and the data strobe signal pin 11. Further, the data strobe signal DSO internally generated in the integrated circuit 110-1 is not exactly synchronized with the data strobe signal DSO internally generated in the integrated circuit 110-2. As a result, the relative timing between the data strobe signals generated from the integrated circuits 110-1 and 110-2 is skewed. Accordingly, the data strobe signal DQS may not be synchronized to capture the data in time. That is, when the data is read out from the conventional semiconductor memory device shown in FIG. 1, even though two data strobe signals are generated from the two integrated circuits, only one data strobe signal may be output from the semiconductor memory device through the data strobe signal input and output pin 11 at a time. Accordingly, the timing for outputting the data strobe signal may not be synchronized with the timing for outputting the data.

SUMMARY OF THE INVENTION

[0016] In an effort to overcome the problems described above, in one embodiment of the present invention a semiconductor memory device having two, or more than two, integrated circuits in one package, is capable of eliminating skewing of data strobe signals.

[0017] In accordance with one aspect of the present invention, the present embodiments exemplify a semiconductor memory device comprising at least one data input/output reference signal input and output pin, and a plurality of integrated circuits, each integrated circuit having a data input/output reference signal input and output buffer with a selectable output disable capability, each such buffer connected to the data input/output reference signal input and output pin. In some embodiments, the selectable output disable capability is provided by a severable fuse on each integrated circuit that can be severed to disconnect the output buffer of the data input/output reference signal input and output buffer from the path to the data input/output reference signal input and output pin. In other embodiments, the selectable output disable capability is provided by a control circuit that can prevent an internally generated data input/output reference signal from activating the output buffer of the data input/output reference signal input and output buffer.

[0018] In another aspect of the present invention, integrated circuits for use in a semiconductor memory device such as just described are described. For instance, such an integrated circuit can comprise an output buffer to buffer an internally generated data input/output reference signal to be output when the integrated circuit outputs data, and means for disabling output of the internally generated data input/output reference signal such that the internally generated data input/output reference signal is not output when the integrated circuit outputs data. The disabling means are exemplified, e.g., by the selectable output disable capabilities described above.

[0019] In yet another aspect of the invention, the described embodiments provide methods of outputting, out of the semiconductor memory device, a data input/output reference signal, e.g., the data strobe signal generated from a DDR RAM. For instance, a method is disclosed for outputting a data input/output reference signal in a semiconductor memory device having at least one data input/output reference input and output pin and a plurality of integrated circuits connected to that pin, the method comprising controlling the integrated circuits such that when the semiconductor memory device is expected to output the data input/output reference signal, only one of the integrated circuits generates the data input/output reference signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] These and other features and advantages of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows when taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which:

[0021] FIG. 1 illustrates a block diagram of a conventional semiconductor memory device;

[0022] FIG. 2 illustrates a block diagram of a semiconductor memory device in accordance with the present invention;

[0023] FIG. 3 illustrates circuit diagrams of a data strobe signal input and output buffer and a control circuit contained in the semiconductor memory device in accordance with the present invention;

[0024] FIG. 4 illustrates a circuit diagram of a control signal generating circuit in accordance with one example of the present invention;

[0025] FIG. 5 illustrate a circuit diagram of a control signal generating circuit in accordance with another example of the present invention; and

[0026] FIG. 6 illustrates a circuit diagram of a data strobe signal input and output buffer in accordance with the present invention.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

[0027] Reference will now be made in detail to preferred embodiments of the present invention, an example of which is illustrated in the accompanying drawings.

[0028] FIG. 2 illustrates a block diagram of a semiconductor memory device 200 in accordance with an embodiment of the present invention. The semiconductor memory device includes: a first integrated circuit 210-1 and a second integrated circuit 210-2, each of which may be a synchronous DDR RAM; a data strobe signal input and output pin 11; and data input and output pins 13-1 and 13-2. The first and second integrated circuits 210-1 and 210-2 include data strobe signal pads 12-1 and 12-2, data strobe signal input and output buffers 216-1 and 216-2, control circuits 20-1 and 20-2, data input and output pads 14-1 and 14-2, and data input and output buffers 18-1 and 18-2, respectively. The data strobe signal input and output pin 11 is electrically and commonly connected to the data strobe signal input and output pads 12-1 and 12-2 in the first and second integrated circuits 210-1 and 210-2. The data input and output pins 13-1 and 13-2 are connected to the data input and output pads 14-1 and 14-2, respectively.

[0029] The control circuits 20-1 and 20-2 provided in the semiconductor memory device shown in FIG. 2 are not present in the conventional semiconductor memory device shown in FIG. 1.

[0030] Functions and operations of each block with like reference in FIG. 1 and FIG. 2 are the same.

[0031] The control circuits 20-1 and 20-2 control the data strobe signal input and output buffers 216-1 and 216-2, respectively, thereby controlling enabling and disabling of the data strobe signals.

[0032] Semiconductor memory device 200 generates one data strobe signal DSQ by controlling the data strobe signal input and output buffers 216-1 and 216-2 using the control circuits 20-1 and 20-2.

[0033] For example, in one configuration, the data strobe signal generated under the control of the control circuit 20-1 from DQSB 216-1, in first integrated circuit 210-1, is output through the data strobe signal input and output pad 12-1 and the data strobe signal input and output pin 11 out of the semiconductor memory device. At the same time, control circuit 20-2 prevents DQSB 216-2 from outputting the data strobe signal generated from the second integrated circuit 10-2 to input and output pad 12-2.

[0034] FIG. 3 illustrates circuit diagrams of a data strobe signal input and output buffer 216-1 and a control circuit 20-1 in accordance with an embodiment of the present invention. DQSB 216-1 comprises a data strobe signal input buffer 32 and a data strobe signal output buffer 34. Control circuit 20-1 comprises a control signal generating circuit 22, inverters I1, I2 and I3, a NOR gate NOR and a NAND gate NA. The data strobe signal input buffer 32 comprises a PMOS transistor P1 and a NMOS transistor N1. The data strobe signal output buffer 34 comprises a PMOS transistor P2 and a NMOS transistor N2.

[0035] Operation of the circuit in FIG. 3 is described below.

[0036] When a control signal CON output from the control signal generating circuit 22 is set to a logic “high” level and the data strobe output signal DSO has a logic “high” level, operation of the circuit in FIG. 3 is as follows:

[0037] The inverter I1 inverts the logic level of the control signal CON, thereby generating a signal of logic “low” level. A first circuit comprising the NOR gate NOR and inverter I2 generates a logic “high” level signal in response to a logic “high” level at the data strobe output signal DSO. A second circuit comprising the NAND gate NA and inverter I3 generates a logic “high” level signal in response to a logic “high” level at the data strobe output signal DSO and the control signal CON at a logic “high” level. Thus, the PMOS transistor P2 turns off and the NMOS transistor N2 turns on, thereby generating a data strobe signal DQS of logic “low” level.

[0038] When the control signal CON maintains a logic “high” level and the data strobe output signal DSO has logic “low” level, operation of the circuit in FIG. 3 is as follows:

[0039] The first circuit comprising the NOR gate NOR and the inverter I2 generates a logic “low” level signal in response to a logic “low” level at the output of the inverter I1 and a logic “low” level for the data strobe output signal DSO. The second circuit comprising the NAND gate NAND and the inverter I3 generates a logic “low” level signal in response to a logic “low” level at the data strobe output signal DSO. Then, the PMOS transistor P2 turns on and the NMOS transistor N2 turns off, thereby generating a data strobe signal DQS of logic “high” level.

[0040] Further, when the control signal CON is set to a logic “low” level and the data strobe output signal DSO has either a logic “low” level or a logic “high” level, operation of the circuit in FIG. 3 is as follows:

[0041] The inverter I1 inverts the logic level of the control signal CON and generates a logic “high” level signal. The first circuit comprising the NOR gate NOR and the inverter I2 generates a logic “high” level signal in response to logic “high” level on the data strobe output signal DSO. The second circuit comprising the NAND gate NA and the inverter I3 generates a logic “low” level signal in response to a logic “low” level on the control signal CON. Thus, the PMOS transistor P2 and the NMOS transistor N2 are turned off and the data strobe signal DQS is not generated.

[0042] Summarizing, when the control signal CON is set to a logic “high” level, logic “high” level or a logic “low” level for the data strobe signal DQS is generated depending upon the logic level of the data strobe output signal DSO. When the control signal CON is set to logic “low” level, however, the data strobe signal DQS is not generated regardless of the data strobe output signal DSO logic level.

[0043] FIG. 4 illustrates a circuit diagram for the control signal generating circuit 22 shown in FIG. 3. The control signal generating circuit 22 comprises three inverters I4, I5 and I6, a PMOS transistor P3, two NMOS transistors N3 and N4, and a fuse F1.

[0044] Upon power-up, a power up signal PVCCH rises from a logic “low” level to a logic “high” level.

[0045] With the fuse F1 intact, the inverter I4 inverts the logic level of the power-up signal PVCCH, thereby generating an inverted signal. That is initially, when the power-up signal PVCCH has logic “low” level, the inverter generates a logic “high” level signal. The PMOS transistor P3 is turned off and the NMOS transistor N3 is turned on so as to transmit a logic “low” level to a node A. The inverters I5 and I6 buffer the logic “low” level signal transmitted via the node A and generate a control signal CON with a logic “low” level. At this time, the NMOS transistor N4 is turned on due to the logic “high” level output signal of the inverter I5, so that the node A maintains a logic “low” level. Then, when the power-up signal PVCCH transitions to a logic “high” level, the inverter I4 inverts the logic level of the power-up signal and generates a logic “high” level signal. Thus, the PMOS transistor P3 turns on and the NMOS transistor N3 turns off, so as to transmit the logic “high” level to node A. The inverters I5 and I6 buffer the logic “high” level signal transmitted from the node A and generate a control signal of logic “high” level.

[0046] With the fuse F1 cut, when the power-up signal PVCCH has a logic “low” level, the inverter I4 inverts the logic level of the power-up signal PVCCH and generates a logic “high” level. The PMOS transistor P3 is turned off and the NMOS transistor N3 is turned on to transmit a logic “low” level to node A. Thus the control signal CON with a logic “low” level is generated by the control signal generating circuit 22. When the power-up signal PVCCH transitions to logic “high” level, however, the inverter I4 inverts the logic level of the power-up signal PVCCH and transmits a logic “low” level to P3 and N3, turning on PMOS transistor P3. At this time, however, the node A maintains the logic “low” level because the fuse F is cut. Accordingly, the control signal CON maintains a logic “low” level with the fuse cut.

[0047] FIG. 5 illustrates a circuit diagram for the control signal generating circuit in accordance with another example of the present invention. The control signal generating circuit comprises a pad 40, two PMOS transistors P4 and P5 and inverters I7 and I8.

[0048] Operation of the circuit in FIG. 5 will be described below.

[0049] When the pad 40 is open, the PMOS transistors P4 and P5 are turned on, thereby transmitting a power supply voltage Vcc to a node B. The inverters I7 and I8 buffer the power supply voltage at node B and generate the control signal CON with a logic “high” level.

[0050] When the pad 40 is connected to a ground voltage, the node B is pulled to the ground voltage. Inverters I7 and I8 buffer the ground voltage at node B and generate the control signal CON with the logic “low” level.

[0051] That is, with the pad 40 being open, control signal CON is set to a logic “high” level; with the pad 40 connected to ground voltage, control signal CON is set to a logic “low” level.

[0052] FIG. 6 illustrates a circuit diagram for a data strobe signal input and output buffer 216-1 in accordance with another example of the present invention. The data strobe signal input buffer 50 comprises a PMOS transistor P6 and a NMOS transistor N5, and the data strobe signal output buffer 52 comprises a PMOS transistor P7, a NMOS transistor N6, and a fuse F2.

[0053] Operation of the data strobe signal input and output buffer shown in FIG. 6 will be described below.

[0054] The data strobe signal input buffer 50 buffers the externally input data strobe signal DQS to generate a data strobe input signal DSI as an input to the integrated circuits.

[0055] When the fuse F2 is intact, the data strobe signal output buffer 52 buffers the internally generated data strobe output signal DSO to generate the data strobe signal DQS. When the fuse F2 is cut, the data strobe signal DQS is not generated.

[0056] The data strobe signal input and output buffer shown in FIG. 6 may control enabling and disabling of the data strobe signal without additional control circuits 20-1 and 20-2.

[0057] As illustrated above, the present invention provides a semiconductor memory device capable of generating and outputting, from one of several integrated circuits, a data strobe signal while disabling the other data strobe signals output from the other integrated circuits contained in the semiconductor memory device. This single data strobe signal is output through the data strobe signal input and output pin of the semiconductor memory device.

[0058] Although the description above relates to a semiconductor memory device containing two integrated circuit in one package, the present invention is also applicable to a semiconductor memory device having more than two integrated circuits in the same package.

[0059] While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor memory device comprising: at least one data input/output reference signal input and output pin; and a plurality of integrated circuits, each integrated circuit having a data input/output reference signal input and output buffer with a selectable output disable capability, each such buffer connected to the data input/output reference signal input and output pin.

2. The semiconductor memory device of claim 1, each of the integrated circuits having a reference output disable fuse, wherein the selectable output disable capability on each integrated circuit has a disable state that depends on whether or not the reference output disable fuse is severed.

3. The semiconductor memory device of claim 2, wherein the reference output disable fuses on all but one of the integrated circuits are set to force the disable state on their respective integrated circuits.

4. The semiconductor memory device of claim 2, wherein on each integrated circuit, the data input/output reference signal input and output buffer comprises an output buffer, the output buffer having an output connected through the reference output disable fuse to the data input/output reference signal input and output pin.

5. The semiconductor memory device of claim 1, wherein on each integrated circuit, the data input/output reference signal input and output buffer comprises an output buffer to buffer an internally generated data input/output reference signal, each integrated circuit further comprising a control circuit to disable or enable the internally generated data input/output reference signal from reaching the output buffer, depending on the state of an output disable control signal.

6. The semiconductor memory device of claim 5, wherein on each integrated circuit the output buffer includes: a first pull-up transistor for pulling up the data input/output reference signal in response to a first drive signal generated by the control circuit; and a first pull-down transistor for pulling down the data input/output reference signal in response to a second drive signal generated by the control circuit.

7. The semiconductor memory device of claim 6, wherein the control circuit includes drive signal generating means for turning off the first pull-up transistor and the first pull-down transistor by setting the first and second drive signals to turn off the first pull-up transistor and first pull-down transistors in response to a first state of the output disable control signal, and outputting the internally generated data input/output reference signal as the first and second drive signals in response to a second state of the output disable control signal.

8. The semiconductor memory device of claim 7, further comprising a control signal generating circuit to generate the output disable control signal.

9. The semiconductor memory device of claim 8, the control signal generating circuit comprising: a first inverter to invert a logic level of a power-up signal; a second pull-up transistor connected between a power supply voltage and a first node to pull up the first node in response to an output signal of the first inverter; a fuse connected between the first node and a second node; a second pull-down transistor connected between the second node and a ground voltage to pull down the second node in response to the output signal of the first inverter; second and third inverters connected in series to buffer the signal appearing at the second node and generate the output disable control signal; and a third pull-down transistor connected between the second node and the ground voltage to pull down the second node in response to an output of the second inverter.

10. The semiconductor memory device according to claim 9, wherein the power-up signal transitions from a first state to a second state upon power-up of the semiconductor memory device.

11. The semiconductor memory device of claim 8, wherein the control signal generating circuit includes: a pad; a third pull-up transistor connected between a power supply voltage and the pad; and buffer circuitry to buffer the signal appearing at the pad and generate the output disable control signal.

12. The semiconductor memory device of claim 11, wherein: one logic level for the output disable control signal is attained on at least one of the integrated circuits by externally floating the pad on that integrated circuit or connecting the pad on that integrated circuit to the power supply voltage; and another logic level for the output disable control signal is attained on at least one other of the integrated circuits by connecting the pad on that other integrated circuit to a ground voltage.

13. A method for outputting a data input/output reference signal in a semiconductor memory device having at least one data input/output reference input and output pin and a plurality of integrated circuits connected to that pin, the method comprising controlling the integrated circuits such that when the semiconductor memory device is expected to output the data input/output reference signal, only one of the integrated circuits generates the data input/output reference signal.

14. An integrated circuit comprising: an output buffer to buffer an internally generated data input/output reference signal to be output when the integrated circuit outputs data; and means for disabling output of the internally generated data input/output reference signal such that the internally generated data input/output reference signal is not output when the integrated circuit outputs data.

15. The integrated circuit of claim 14, wherein the disabling means comprises a cuttable fuse integrated on the circuit.

16. The integrated circuit of claim 14, wherein the disabling means comprises a control circuit to disable or enable the internally generated data input/output reference signal from reaching the output buffer, depending on the state of an output disable control signal.

17. The integrated circuit of claim 16, wherein the output buffer includes: a first pull-up transistor for pulling up the data input/output reference signal in response to a first drive signal generated by the control circuit; and a first pull-down transistor for pulling down the data input/output reference signal in response to a second drive signal generated by the control circuit.

18. The integrated circuit of claim 17, further comprising a control signal generating circuit to generate the output disable control signal.

19. The integrated circuit of claim 18, the control signal generating circuit comprising: a first inverter to invert a logic level of a power-up signal; a second pull-up transistor connected between a power supply voltage and a first node to pull up the first node in response to an output signal of the first inverter; a fuse connected between the first node and a second node; a second pull-down transistor connected between the second node and a ground voltage to pull down the second node in response to the output signal of the first inverter; second and third inverters connected in series to buffer the signal appearing at the second node and generate the output disable control signal; and a third pull-down transistor connected between the second node and the ground voltage to pull down the second node in response to an output of the second inverter.

20. The integrated circuit of claim 18, wherein the control signal generating circuit includes: a pad; a third pull-up transistor connected between a power supply voltage and the pad; and buffer circuitry to buffer the signal appearing at the pad and generate the output disable control signal.