1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly relates to a semiconductor memory device that includes sense amplifiers.
2. Description of Related Art
In semiconductor memory devices such as a DRAM (Dynamic Random Access Memory), sense amplifiers that amplify a signal read from a memory cell to a bit line are employed. However, the signal read to the bit line is very weak, and thus amplification by the sense amplifiers takes a relatively longer period of time. This causes a problem that an access speed is rate-controlled during random access.
As a technique to improve sensing speed, an overdrive potential is used. See Japanese Patent Application Laid-open No. 2000-22108. This is a technique in which an overdrive potential higher than a higher-side write potential is supplied to a sense amplifier at an initial stage of a sense operation, thereby improving the sensing speed.
However, during a sense operation, a large number of sense amplifiers are simultaneously activated, and thus there is a problem that the overdrive potential is easily fluctuated. To solve such a problem, it is possible to adopt a method of increasing the size of a power supply circuit that produces the overdrive potential. However, this method is not preferable because its chip area is significantly increased.
Alternatively, it is also possible to adopt a method of using a stabilizing capacitance to stabilize the overdrive potential. However, to stabilize the overdrive potential by solely using a stabilizing capacitance, a very large capacitance is required to a stabilizing capacitor. Thus, the chip area is greatly increased also in this case. Further, at an initial stage of the sense operation, a lower-side write potential is fluctuated similarly to the overdrive potential, and thus, in order that a fluctuation amount of the lower-side write potential is set equal to that of the overdrive potential, it is necessary to add a stabilizing capacitance having the same capacitance value to the lower-side write potential. As a result, the chip area is further increased.
Such problems similarly occur not only in a sense amplifier in which an overdrive operation is performed, but also in a sense amplifier in which any overdrive operation is not performed. That is, even in a sense amplifier in which any overdrive operation is not performed, a large number of sense amplifiers are simultaneously activated during its sense operation. Thus, various drive potentials are easily fluctuated.
The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part.
In one embodiment, there is provided a semiconductor memory device comprising: a sense amplifier that amplifies a potential difference appearing in a pair of bit lines; a first power supply wiring that supplies a first potential via a first driver to the sense amplifier; a second power supply wiring that supplies a second potential via a second driver to the sense amplifier; and a stabilizing capacitance arranged between the first power supply wiring and the second power supply wiring.
In the present invention, it is preferred that there is further provided a third power supply wiring that supplies a third potential via a third driver to the sense amplifier, the first potential is a lower-side write potential of the bit lines, the third potential is a higher-side write potential of the bit lines, and the second potential is an overdrive potential higher than the higher-side write potential.
According to the present invention, the stabilizing capacitance is arranged between the first and second potentials as drive potentials of the sense amplifier. Accordingly, it is not necessary to separately arrange the stabilizing capacitance to each of the potentials. Further, capacitance values applied to these potentials inevitably match, and thus fluctuation of the potential at an initial stage of a sense operation is offset. With this configuration, it becomes possible to effectively suppress fluctuation of a sense-amplifier drive potential while suppressing an increase in chip area to minimum.
Particularly, when the stabilizing capacitance is arranged between the first power supply wiring that supplies the lower-side write potential and the second power supply wiring that supplies the overdrive potential, it becomes possible to effectively suppress the fluctuation of the overdrive potential.
The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings.
The semiconductor memory device according to the present embodiment is a DRAM. As shown in
As shown in
the higher-side write potential or the lower-side write potential is supplied to the cell capacitor C according to data to be stored when writing data in the memory cell MC0. As described later, in the present embodiment, the higher-side write potential is written as VARY, and is set to 1.2 V, for example. The lower-side write potential is written as VSSA, and is set to 0 V (ground potential), for example. Driving the bit lines BL0 and BL1 along with writing such data is performed by the sense amplifier SA.
On the other hand, when reading the data from the memory cell MC0, a bit line BL is precharged to an intermediate potential, i.e., (VARY−VSSA)/2 (such as 0.6 V. Hereinafter, “VBLP”), and thereafter, the cell transistor Tr is turned on. Thereby, when the higher-side write potential has been stored in the cell capacitor C, the potential of the bit line BL0 slightly rises from the intermediate potential VBLP. In contrast, when the lower-side write potential has been stored in the cell capacitor C, the potential of the bit line BL0 slightly falls from the intermediate potential VBLP. Thus, a very small potential difference thus occurring between the bit lines BL0 and BL1 is amplified by the sense amplifier SA.
As shown in
As shown in
By such a flip-flop structure, when the potential difference occurs in a bit line pair of BL0 and BL1 in a state that the higher-side-potential drive wiring SAP and the lower-side-potential drive wiring SAN are supplied with a predetermined potential, the potential of the higher-side-potential drive wiring SAP is supplied to one of the bit line pair, and the potential of the lower-side-potential drive wiring SAN is supplied to the other one of the bit line pair. As described later, in the present embodiment, the higher-side-potential drive wiring SAP is supplied with the higher-side write potential VARY, and the lower-side-potential drive wiring SAN is supplied with the lower-side write potential VSSA. Further, at an initial stage of the sense operation, the higher-side-potential drive wiring SAP is temporarily supplied with an overdrive potential VOD higher than the higher-side write potential VARY.
Referring back to
Between the higher-side-potential drive wiring SAP and a power supply wiring 22, a driver 12 is connected. The power supply wiring 22 is supplied with the higher-side write potential VARY. As a result, when the driver 12 is turned on, the higher-side-potential drive wiring SAP is supplied with the higher-side write potential VARY. In the present embodiment, the driver 12 is configured by a P-channel MOS transistor. Accordingly, the driver 12 is turned on when a control signal 12a becomes a low level.
Between the higher-side-potential drive wiring SAP and a power supply wiring 23, a driver 13 is connected. The power supply wiring 23 is supplied with the overdrive potential VOD. As a result, when the driver 13 is turned on, the higher-side-potential drive wiring SAP is supplied with the overdrive potential VOD. In the present embodiment, the driver 13 is configured by a P-channel MOS transistor. Accordingly, the driver 13 is turned on when a control signal 13a becomes a low level. The overdrive potential VOD is generated by a VOD generator described later, and its potential is set to 1.45 V, for example.
These control signals 11a to 13a are generated by a control circuit 10 shown in
As shown in
Cvod≧(VARY−VBLP)·Cb/(VOD−VARY) (1)
where Cb represents all capacitance values of bit lines simultaneously selected within a bank, and Cvod represents a capacitance value of the stabilizing capacitance 30 per each bank. When the equation (1) is satisfied, the fluctuation at an initial stage of the sense operation is almost completely offset.
The method of configuring the stabilizing capacitance 30 on a chip is not particularly limited. However, it is preferred to utilize a gate capacitance of an MOS transistor. The reason for this is that when the gate capacitance is used, it becomes possible to secure a large capacitance value with a relatively small area. It is particularly preferred to utilize a trench gate capacitance utilizing a trench formed on a semiconductor substrate.
First, before a time t10, the bit line pair of BL0 and BL1 are precharged to the intermediate potential VBLP. When the row address ADD reaches a predetermined value at the time t10, the word line WL0 corresponding thereto is ascended from a negative potential Vkk. A level of the activated word line WL0 is enhanced to a potential (VPP) much higher than the overdrive potential VOD. Thereby, the cell transistor Tr included in the memory cell MC is turned on, and thus the cell capacitor C and the bit line BL0 are short-circuited. As a result, the potential of the bit line BL0 is changed. Before the time t10, the control signals 11a to 13a are in an inactive state. Accordingly, all the drivers 11 to 13 are turned off.
Subsequently, when it is a time t11, the control circuit 10 activates the control signals 11a and 13a to a high level and a low level, respectively. Thereby, the drivers 11 and 13 are simultaneously turned on, and thus the lower-side write potential VSSA is supplied to the lower-side-potential drive wiring SAN, and the overdrive potential VOD is supplied to the higher-side-potential drive wiring SAP. In this case, the lower-side-potential drive wiring SAN and the higher-side-potential drive wiring SAP are connected with a large number of sense amplifiers SA, and thus, when the driver 11 is turned on, the power supply wiring 21 attempts to come up to a potential higher than the lower-side write potential VSSA, and when the driver 13 is turned on, the power supply wiring 23 attempts to fall down to a potential lower than the overdrive potential VOD.
However, such power supply fluctuation is suppressed by the stabilizing capacitance 30. That is, one electrode of the stabilizing capacitance 30 is connected to the power supply wiring 21 and the other electrode of the stabilizing capacitance 30 is connected to the power supply wiring 23, and thus, when the potentials of these power supply wirings 21 and 23 are fluctuated in a direction opposite to each other, the fluctuation is offset. As a result, in practice, substantially no fluctuation occurs. Particularly, when the capacitance value of the stabilizing capacitance 30 satisfies the equation (1), the fluctuation is substantially completely offset.
When the lower-side-potential drive wiring SAN and the higher-side-potential drive wiring SAP are thus driven, the sense amplifier SA lifts one of the bit line pair of BL0 and BL1 and lowers the other one. At this time, lifting one of the bit line pair of BL0 and BL1 is performed not by the higher-side write potential VARY but by the overdrive potential VOD higher in potential than the higher-side write potential VARY, and thus a faster sense operation is realized.
Subsequently, when it is a time t12, the control circuit 10 activates the control signal 12a to a low level so that the driver 12 is turned on, and inactivates the control signal 13a to a high level so that the driver 13 is turned off. Thereby, the higher-side write potential VARY is supplied to the higher-side-potential drive wiring SAP, and thus, one of the bit line pair of BL0 and BL1 is driven by the higher-side write potential VARY and the other one is driven by the lower-side write potential VSSA. Accordingly, data of the memory cell MC0 destructed by reading is restored.
It is preferred that in the wiring network shown in
The present embodiment provides a semiconductor memory device as an example in which the sense amplifier does not perform any overdrive operation. A driver 51 is connected between the lower-side-potential drive wiring SAN and a power supply wiring 61, and a driver 52 is connected between the higher-side-potential drive wiring SAP and a power supply wiring 62. The power supply wiring 61 is supplied with a lower-side write potential VL, and the power supply wiring 62 is supplied with a higher-side write potential VH. In this case, the potentials VH and VL can optionally be an internal power supply produced inside the semiconductor memory device, or an external power supply supplied from outside the semiconductor memory device.
Also in the present embodiment, between the power supply wiring 61 and the power supply wiring 62, the stabilizing capacitance 30 is connected. Thereby, when the drivers 51 are simultaneously turned on to activate the sense amplifier SA, the fluctuation of the lower-side write potential VL and the fluctuation of the higher-side write potential VH are offset by the stabilizing capacitance 30. In this way, it is also possible to apply the present invention to a semiconductor memory device using a sense amplifier that does not perform any overdrive operation.
While preferred embodiments of the present invention have been described above, the invention is not limited to the above embodiments. Various modifications can be made without departing from the scope of the present invention, and needless to mention, these modifications are also included within the scope of the invention.
Number | Date | Country | Kind |
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2008-275979 | Oct 2008 | JP | national |