Semiconductor memory device including non-volatile transistor for storing data in a bistable circuit

Abstract

A non-volatile random access memory device includes a plurality of memory cells, each of which has a bistable (flip-flop) circuit which acts as an ordinary random access memory cell and at least one non-volatile memory transistor. The bistable circuit has two output terminals (a true output terminal and a complementary output terminal). One of the two output terminals is coupled to a control electrode of the non-volatile memory transistor, and the other output terminal is coupled to the drain of the non-volatile memory transistor. The source of the non-volatile memory transistor is coupled to a driving voltage source (e.g. 5 V) via a switching gate which is turned on when a control signal is applied thereto. In a normal operation mode, a normal driving voltage (e.g. 5 V) is supplied to the bistable circuit. On the other hand, when data in the bistable circuit is to be sheltered in the non-volatile memory transistor, a high voltage (e.g. 20 V) is supplied to the bistable circuit, whereby the non-volatile memory transistor stores the data in the bistable circuit. When the data stored in the non-volatile memory transistor is to be returned to the bistable circuit, the switching gate is turned on in response to a control signal. Thus, the data in the non-volatile memory transistor is restored in the bistable circuit. These operations can be easily performed at high speed with simple hardware elements.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory, and more particularly to a memory device having a non-volatile function known as a non-volatile random access memory.

2. Description of the Prior Art

A non-volatile random access memory is a memory which has a conventional random access memorizing function and a non-volatile memorizing function. The non-volatile random access memory operates as a random access memory under normal operating conditions. However, when a driving voltage supplied to the memory device drops or when the power supply is turned off, the information stored in the random access memory circuit is transferred to a non-volatile memory circuit. Thereafter, when the driving voltage recovers or when the power supply is turned on, the information is returned to the random access memory circuit. Thus, the information is kept in the memory without destruction for a long period of time.

In the prior art, many transistor elements are required to constitute the non-volatile random access memory cell. Therefore, it is hard to provide a large capacity memory device. On the other hand, a non-volatile random access memory cell with a small number of transistor elements is proposed in U.S. Pat. No. 4,207,615. This memory cell has a non-volatile MOS transistor between one of a pair of load transistors and one of a pair of driver transistors in a flip-flop type RAM memory cell, and further a depletion transistor is added in parallel to the non-volatile MOS transistor. Therefore, impedance mismatching occurs between the two load stages in the flip-flop cell. As a result, the reading and writing speeds in an ordinary random access operation become slow. Furthermore, the proposed memory cell has a shortcoming in that it is difficult to form the cell by means of a complementary MOS (C-MOS) circuit. Therefore, the power consumption of the overall circuit is unavoidably large. Further, in U.S. Pat. No. 4,132,904 two non-volatile MOS transistors are used as driving MOS transistors in a flip-flop memory cell. However, according to this memory cell, reading operations and writing operations are very complex. Namely, the prior art non-volatile memory devices have disadvantages in that many elements are required to constitute the memory cell and in that complicated operations are required.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a non-volatile random access memory device having a memory cell in which reading and writing operations can be performed at a high speed.

Another object of the present invention is to provide a memory device having a non-volatile memorizating function with small power consumption.

Still another object of the present invention is to provide a semiconductor memory device having a random access function and a non-volatile memorizing function and capable of performing a sheltering operation and a recovering (reproducing) operation in a short period of time.

A semiconductor memory device according to the present invention has a plurality of memory cells on a semiconductor chip. Each memory cell has a bistable (e.g. flip-flop) memory circuit and a non-volatile memory circuit. The bistable memory circuit has two output terminals (a true output terminal and a complementary output terminal) and acts as an ordinary random access memory cell when a driving voltage is supplied thereto. The non-volatile memory circuit has at least one non-volatile memory transistor having a control electrode coupled to one of the two output terminals of the bistable circuit and having one end portion coupled to the other output terminal of the bistable circuit. The other end portion of the non-volatile memory transistor receives the driving voltage via a switching gate circuit which is turned on according to a control signal.

In the present invention, the bistable circuit can act as an ordinary random access memory cell in a normal mode. When data is to be sheltered from the RAM cell to the non-volatile memory transistor, a voltage which is higher than the normal driving voltage and which is supplied externally in addition to the normal driving voltage or generated internally in the chip is applied to the bistable circuit, whereby the data voltage at the output terminals of the bistable circuit becomes high enough to enable the non-volatile memory transistor, and the data of the bistable circuit is stored in the non-volatile memory transistor (a data sheltering operation). By applying the control signal to the switching gate circuit, and by applying the normal driving voltage to the bistable circuit, the data stored in the non-volatile memory transistor is rewritten in the bistable circuit, automatically (a data reproduction operation).

Thus, the present invention provides a nonvolatile random access memory device which can hold the data to be manipulated in the bistable circuit for a long period of time with simple hardware elements. Further, the data sheltering operation and the data reproduction operation can be easily performed at high speed. Moreover, since the non-volatile memory transistor is provided outside of the bistable circuit, a C-MOS type flip-flop circuit can be used as the bistable circuit. Therefore, the power consumption can be remarkably reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a well-known non-volatile memory element;

FIG. 2 is a diagram of the characteristics of the element in FIG. 1;

FIG. 3 is a circuit diagram of a memory cell of an embodiment according to the present invention;

FIG. 4 is a circuit diagram of a memory cell of another embodiment according to the present invention;

FIG. 5 is a timing chart indicating the sheltering and data reproduction operations in the memory cells of FIGS. 3 and 4;

FIG. 6 is a block diagram of a memory device including the memory cells of FIGS. 4 and 5;

FIG. 7 is a circuit diagram of the high voltage generating circuit in FIG. 6; and

FIG. 8 is an operation timing chart of the device of FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Firstly, a non-volatile memory element which may be used in the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 is a crosssectional view of a non-volatile memory transistor. The non-volatile memory transistor of FIG. 1 has an N-type drain region 2 and an N-type source region 3 which are respectively formed in a P-type semiconductor substrate by means of N-type impurity introduction technology. The transistor further has a control gate 7 and a floating gate 8 in a silicon oxide film 4. The floating gate 8 has a bent portion approaching the drain region 2. At the bent portion, at least one portion 9 of the silicon oxide film over the drain region 2 is made selectively thin. As shown in FIG. 1, the control gate 7 and the floating gate 8 are formed so as to cover the channel region between the drain region 2 and the source region 3 and at least one portion of the drain region 2. A drain electrode 5 and a source electrode 6 are connected to the drain and source regions 2 and 3, respectively, and are extended on a field oxide film 4'.

FIG. 2 is a diagram indicating electrical characteristics of the non-volatile memory transistor shown in FIG. 1. The abscissa represents the gate voltage (V.sub.CG) applied to the control gate 7, and the ordinate represents the drain current (I.sub.DS) between the drain region 2 and the source region 3, when a constant voltage is applied to the drain region 2 and when a ground potential is applied to the source region 3. In FIG. 1, when the control gate 7 is grounded and a high voltage is applied to the drain region 2, a strong electric field is created in the thin oxide film portion 9 from the drain region 2 toward the floating gate 8. As a result, holes are injected into the floating gate 8. Thus, an N-type inversion layer tends to be formed in the channel region between the drain and the source regions 2 and 3. Therefore, as shown by the curve 21 of FIG. 2, even if a negative voltage is applied to the control gate 7, the drain current flows through the channel region. This means that the non-volatile memory element has a negative threshold voltage. Hereinafter, this condition is called "erasing" or "clearing."

On the other hand, in a writing operation, a high voltage is applied to the control gate 7 and the drain region is grounded. In this condition a strong electric field is created in the thin oxide film portion 9 from the floating gate 8 toward the drain region 2. As a result, electrons are injected into the floating gate 8 to make it difficult to form an inversion layer in the channel region. Therefore, as shown by the curve 22 of FIG. 2, the threshold voltage becomes a high positive value. This condition may be called the data "1" writing condition.

As described above, binary "1" and "0" data can be stored in the non-volatile memory element shown in FIG. 1. When the stored data is read out of the element, a positive voltage V.sub.1 lower than the threshold voltage as increased by the writing operation may be applied to the control gate 7. If the element is in the erased condition, it turns on and obtains the drain current I.sub.1. If the element is in the written condition, it cannot turn on and the drain current does not flow. That is, the non-conductive condition is maintained.

The non-volatile memory element as described is well known and is disclosed in, for example, Electronics pp. 113-117, Feb. 28, 1980, as applied to an EEPROM (electronically erasable programmable read-only memory).

Preferred embodiments of the present invention will now be described with reference to the drawings. FIG. 3 is a circuit diagram of a memory cell according to a first embodiment of the present invention in which insulating gate field effect transistors (hereinafter referred to as IGFETs) of N-channel type formed on a P-type semiconductor substrate are used.

IGFET T.sub.31 of the depletion type and IGFET T.sub.32 of the enhancement type are connected in series to constitute a first inverter circuit, and IGFET T.sub.33 of the depletion type and IGFET T.sub.34 of the enhancement type are connected in series to constitute a second inverter circuit. The two inverter circuits have their respective inputs and outputs cross-coupled, and constitute a bistable (flip-flop) circuit. The depletion type IGFETs T.sub.31 and T.sub.33 act as loads and are coupled to the first power supply terminal 30. Further, the two output terminals O.sub.1 and O.sub.2 of the first and second inverter circuits are coupled to digit (bit) lines D and D through IGFETs T.sub.35 and T.sub.36 of the enhancement type, respectively. The respective gates of the IGFETs T.sub.35 and T.sub.36 are coupled to a word line W to which a decoded address signal is applied. The respective drains of T.sub.35 and T.sub.36 are coupled to the digit lines D and D to enable data to be written in the bistable circuit or to be read out of the bistable circuit. Complementary data are transferred through the digit lines D and D, respectively. The output terminal O.sub.1 is coupled to the drain of non-volatile memory element M.sub.31 (for example, the element shown in FIG. 1), while the output terminal O.sub.2 is coupled to a control gate of the element M.sub.31. The source of memory element M.sub.31 is coupled to the source of an IGFET T.sub.37 of the enhancement type. The gate of IGFET T.sub.37 receives a control signal R generated at the timing when data is returned (rewritten) into the bistable circuit. The drain of the IGFET T.sub.37 is coupled to a second power supply terminal 32. In this embodiment, a constant voltage (a driving voltage of 5V for instance) may be applied to the second power supply terminal 32.

Firstly, when the non-volatile random access memory cell of FIG. 3 operates as an ordinary static random access memory cell, a voltage (5V) which can drive the first and second inverter circuits is applied to the first power supply terminal 30 as a normal driving voltage. This voltage may be the same as the constant voltage applied to the second power supply terminal 32. At this time, the signal R is not applied to the IGFET T.sub.37. That is, the gate of IGFET T.sub.37 is kept at a low level (ground potential). A normal writing operation is performed in this condition. That is, if the digit lines D and D are at a high level (about 5V) and a low level (0V), respectively, the IGFET T.sub.34 becomes turned on, while the IGFET T.sub.32 becomes turned off. Therefore, the bistable circuit stores data "1". On the other hand, if the digit lines D and D are at the low level and the high level, respectively, the IGFETs T.sub.32 and T.sub.34 are turned on and off, respectively. As a result, data "0" is written in the bistable circuit. In this normal writing operation, though voltages at the output terminals O.sub.1 and O.sub.2 are supplied to the non-volatile memory element M.sub.31, their difference is so small that the electric field created between the drain and the control gate of the element M.sub.31 is weak. Therefore, the "writing" and "erasing" operations in the element M.sub.31 are not performed because of the weak electric field.

The normal reading operation of the bistable circuit is performed by coupling the output terminals O.sub.1 and O.sub.2 to the digit lines D and D, respectively. In order to start the reading operation, the digit lines D and D are precharged at, for example, a high (5V) level by means of a precharge circuit (not shown). Thereafter, the word line W assumes a high level, so that both the IGFETs T.sub.35 and T.sub.36 are turned on. Now, if the bistable circuit stores data "1", the output terminals O.sub.1 and O.sub.2 are at the high level and the low level, respectively. In this condition, the IGFET T.sub.32 is kept in the turned-off state, while the IGFET T.sub.33 is kept in the turned-on state. Therefore, the charge on the digit line D is discharged to ground through the IGFET T.sub.34. However, the charge on the digit line D is not discharged because of the turned-off IGFET T.sub.32. As a result, a high level signal and a low level signal are transferred through the digit lines D and D, respectively, to a sense amplifying circuit (not shown) coupled to both digit lines D and D. Thus, the data "1" can be read out. On the other hand, if data "0" is stored in the bistable circuit, only the charge on the digit line D is discharged to ground through the IGFET T.sub.32. Therefore, the low level signal and the high level signal are transferred to the sense amplifying circuit through the digit lines D and D, respectively. Thus, the data "0" is read out.

As described above, the circuit of FIG. 3 can be operated as an ordinary random access memory cell by maintaining the signal R for data reproduction at the low (ground) voltage level.

Next, a sheltering operation will be described. In this operation, the data in the bistable circuit is transferred to the non-volatile memory element M.sub.31 and is stored therein if the driving voltage is shut off. When the data which is already stored in the bistable circuit is to be sheltered in the non-volatile memory element M.sub.31, a high voltage (e.g. 20V), different from the normal voltage, is supplied to the first power supply terminal 30 to create a strong electric field, as shown in FIG. 5. At this time, the control signal R for data reproduction is at a low (ground) potential. Thus, if data "1" is stored in the bistable circuit, the IGFET T.sub.32 is turned on and the IGFET T.sub.34 is turned off. Therefore, the drain of the element M.sub.31 is kept at the ground potential, while the high voltage (e.g. 20V) is applied to the control gate of the element M.sub.31. Thus, a strong electric field from the control gate toward the drain of the element M.sub.31 is created. As a result, the threshold voltage of the non-volatile memory element M.sub.31 has a positive value as shown in FIG. 2, e.g., per the "writing operation" curve 22 shown in FIG. 2. On the other hand, if the bistable circuit stores data "0", the IGFET T.sub.32 is kept in the turned-off state, while the IGFET T.sub.34 is in the turned-on state. Therefore, to the drain and the control gate of the non-volatile memory element M.sub.31 are applied the high voltage (about 20V) and the ground voltage (0V), respectively. Thus, a strong electric field from the drain toward the control gate is created, so that the threshold level of the element M.sub.31 assumes a negative value, e.g., per the "erasing operation" curve 21 shown in FIG. 2.

As mentioned above, either the "writing operation" or the "erasing operation" can be performed in the non-volatile element M.sub.31 according to the data stored in the bistable circuit. Therefore, when the driving voltage supplied to the memory device drops or is turned off, the data stored in the bistable circuit can be easily held in the non-volatile memory element M.sub.31 by supplying to the first power supply terminal 30 a high voltage which can provide a voltage difference at the output terminals O.sub.1 and O.sub.2 which is high enough to enable the element M.sub.31.

Next, when data reproduction is required after the driving voltage is reinstated or is turned on, a signal R of a high level is applied to the gate of the IGFET T.sub.37. As a result, the source of the nonvolatile memory element M.sub.31 is coupled to the second power supply terminal 32, to which a constant voltage, for example equal to the driving voltage (5V), is supplied. The word line W is held at the low level, and the digit lines D and D are decoupled from the bistable circuit. Further, it is assumed that the threshold level of the first inverter circuit (T.sub.31 and T.sub.32) is higher than that of the second inverter circuit (T.sub.33 and T.sub.34). In this condition, when the driving voltage (e.g. 5V) is supplied at the first power supply terminal 30, potentials at the output terminals O.sub.1 and O.sub.2 simultaneously rise. If a writing operation is performed in the non-volatile memory element M.sub.31, this element does not turn on as shown in FIG. 2 because of the high positive threshold level. The IGFET T.sub.34 of the second inverter circuit (with the low threshold level) is turned on faster than the IGFET T.sub.32 of the first inverter circuit. Consequently, the potential at the output terminal O.sub.2 assumes the low (ground) level, while the turned-off state of the IGFET T.sub.32 is maintained. As a result, the output terminal O.sub.1 assumes a high level, and the output terminal O.sub.2 assumes a low level. Thus, data "1" is restored in the bistable circuit. On the other hand, when the erasing operation has been performed in the non-volatile memory element M.sub.31, this element M.sub.31 turns on since the voltage at the control gate becomes higher than the threshold level of the IGFET M.sub.31. Therefore, the IGFET T.sub.32 turns on because the constant voltage is applied to the gate of the IGFET T.sub.32. As a result, the output terminal O.sub.1 assumes the low level, while the output point O.sub.2 assumes the high level. That is, data "0" is restored in the bistable circuit.

As described in the foregoing, the non-volatile random access memory cell shown in FIG. 3 can act as a normal random access memory cell when a first driving voltage (e.g. 5V) is supplied at the first power supply terminal 30 and when the signal R is not applied to the IGFET T.sub.37. The cell can also act as a non-volatile memory cell when a second, higher driving voltage (e.g. 20V) is supplied to the first power supply terminal 30. Further, when a driving voltage is resupplied to the first power supply terminal 30 after being cut off and when the switching gate T.sub.37 is turned on, data sheltered in the non-volatile memory element M.sub.31 is restored to the bistable circuit. According to this embodiment, these operations can be easily performed by a simple circuit in which only one non-volatile memory element (for example, that shown in FIG. 1) and a switching gate are added to an ordinary static memory cell. Further, the sheltering operation can be quickly performed by supplying a high driving voltage at the first power supply terminal 30. Moreover, during data reproduction (restoring data to the bistable circuit), the signal R is only applied to the switching gate temporarily. Therefore, the controlability of the cell is very high.

FIG. 4 illustrates a non-volatile random access memory cell according to another embodiment of the present invention. In this embodiment, well-known complementary IGFETs (C-MOS FETs) are used in the ordinary static memory cell. As shown in FIG. 4, a first inverter circuit includes a P channel MOS FET T.sub.41 and an N channel MOS FET T.sub.42, while a second inverter circuit includes a P channel MOS FET T.sub.43 and an N channel MOS FET T.sub.44.

These two C-MOS inverter circuits are coupled to each other in a flip-flop manner. A first output O.sub.3 and a second output O.sub.4 are coupled to the digit lines D and D, respectively, via N channel MOS FETs T.sub.45 and T.sub.46 used as transfer gates. These two FETs T.sub.45 and T.sub.46 are connected to the word line W. A non-volatile memory element M.sub.41, which is the same as the element M.sub.31 of FIG. 3, and an N channel MOS FET T.sub.47 used as a switching gate are also provided. The drain of the element M.sub.41 is connected to the second output O.sub.4, and a control gate of element M.sub.41 is connected to the output O.sub.3. A control signal R is applied to the gate of the FET T.sub.47, whose drain is coupled to the second power supply terminal 32. The two inverter circuits constitute a bistable circuit which acts as an ordinary random access memory cell and selectively receives a driving voltage (e.g. 5V) and a high voltage (e.g. 20V) at the first power supply terminal 30. In this embodiment, the driving voltage (5V) is applied to the second power supply terminal 32.

The non-volatile random access memory cell of FIG. 4 operates the same as the memory cell of FIG. 3. That is, in a normal mode, the driving voltage (5V) is applied to the first power supply terminal 30 and the control signal R is not applied to the FET T.sub.47. In this condition, when the word line W assumes a high level, reading operations and writing operations are selectively performed. Further, when the high voltage (20V) is applied to the first terminal 30 and when the switching gate (T.sub.47) is turned off, the data in the bistable circuit is sheltered and stored in the element M.sub.41. When the driving voltage is resupplied to the first terminal 30 and when the control signal is applied to the FET T.sub.47, the data stored in the element M.sub.41 is rewritten in the bistable circuit. The timing chart of these operations is the same as that in FIG. 5.

FIG. 6 is a circuit diagram of a principal portion of a non-volatile random access memory provided on a single semiconductor chip 60. On the chip 60, n.times.m memory cells are arranged in a matrix array. Each cell is the same as that shown in either FIG. 3 or FIG. 4. Address bits are applied to a plurality of address pins; one part being used as word select signals, and the other part being used as column select signals. An X decoder and driver 61 receives the word select bits and produces a word select signal. When n cells (C.sub.11 to C.sub.1n) coupled to a selected word line (e.g. W.sub.1) are selected, the data stored in the respective cells is simultaneously read out to the digit lines D.sub.1 and D.sub.1, D.sub.2 and D.sub.2, . . . , D.sub.n and D.sub.n, respectively, in a normal read operation mode. A Y decoder and driver 62 select one pair of the digit lines according to the column select bits. The data on the selected digit line pair is amplified by a sense circuit 63 and are output to an output terminal 64. In a normal write operation, data is applied to a write control circuit 66 through a data input terminal 65 and is written into a memory cell selected by the X and Y decoders and drivers. These operations may be the same as that of an ordinary read-write memory device. The chip 60 has a driving voltage supply terminal 67 and a ground voltage supply terminal 68, and further has a high voltage (20V) supply terminal 69 and a control signal input terminal 70. FIG. 6 does not expressly show the ground line or the line for supplying the constant voltage (5V) to the switching gate (T.sub.37, T.sub.47).

In the case of the sheltering operation, in FIG. 6, the X and Y decoders and drivers 61 and 62 are deactivated, and the high voltage (20V) is applied to all memory cells through a select circuit 71. As a result, the data of all of the bistable circuits are simultaneously stored in the respective non-volatile memory elements (M.sub.31, M.sub.41). Thereafter, when the data in all the non-volatile memory elements are to be rewritten in the respective bistable circuits, the select circuit 71 selects the terminal 67 to apply the driving voltage to each memory cell, and the control signal R is applied to all switching gates through the terminal 70. Thus, the sheltered data are simultaneously restored in the respective bistable circuits. In this operation, if a power-on reset circuit 72 is provided on the chip 60, a reset signal generated from the circuit 72 may be used as the control signal. Therefore, the control signal input terminal 70 can be omitted.

Further, if a high voltage generating circuit 73 as shown in, for example, FIG. 7 is provided on the chip 60, the terminal 69 through which a high voltage is supplied to the chip can be omitted. The high voltage generating circuit shown in FIG. 7 includes an N channel IGFET T.sub.71 whose drain electrode is coupled to the driving voltage source (e.g. the terminal 67 in FIG. 6), an N channel IGFET T.sub.72 whose drain electrode is coupled to a source electrode of the IGFET T.sub.71, an N channel depletion type IGFET T.sub.73 whose drain electrode is coupled to the driving voltage source and whose source electrode is coupled to the first power supply terminal 30 in FIGS. 3 and 4, and a charging circuit 70' in which a plurality of enhancement type IGFETs, whose gate electrodes and drain electrodes are connected to each other, are connected in series. Connection points B.sub.1 to B.sub.2n of each IGFET are coupled to capacitors C.sub.1 to C.sub.2n, respectively. The IGFET T.sub.71 receives a control signal A, which assumes a high level when the sheltering operation is performed, at its gate. The IGFET T.sub.72 receives an inverted control signal A at its gate. The IGFET T.sub.73 receives the inverted control signal A at its gate.

It is assumed that a constant voltage (V.sub.CC =5V) is used as the driving voltage in FIG. 7. A timing chart of the operation of the device of FIG. 7 is shown in FIG. 8.

When the non-volatile random access memory of FIG. 6 acts in the normal mode and in the data reproduction mode, the control signal A assumes a low level and the inverted control signal A assumes a high level. As a result, the charging circuit 70' is inactivated, and the depletion type IGFET T.sub.73 is turned on. Therefore, the voltage V.sub.CC is supplied at the first power supply terminal 30.

On the other hand, when the sheltering operation is required, the control signal A assumes a high level and the inverted signal A assumes a low level. Consequently, the IGFET T.sub.71 is turned on, while the IGFET T.sub.72 is turned off. In this condition, when a clock signal .phi. assumes a high level, the potentials on contact portions coupled to capacitors C.sub.1, C.sub.3, . . . , C.sub.2n-1 rise, and, therefore, the IGFETs whose gates are coupled to the capacitors C.sub.1, C.sub.3, . . . C.sub.2n-1 are biased in a forward direction. As a result, positive potentials are simultaneously transferred from the nodes B.sub.1, B.sub.3, . . . , B.sub.2n-1 to the nodes B.sub.2, B.sub.4, . . . B.sub.2n, respectively. Thereafter, a clock signal .phi..sub.2 assumes a high level. Then, the potential levels at the nodes B.sub.2, B.sub.4, . . . , B.sub.2n rise, respectively. Therefore, the potential levels at the nodes B.sub.1, B.sub. 3, . . . B.sub.2n-1 become high as shown in FIG. 8. Thus, the source voltage of the IGFET T.sub.73 becomes higher in a stepwise manner. In this state, the IGFET T.sub.73 is turned off. Therefore, the source potential of the IGFET T.sub.73 is not transferred to the constant voltage source V.sub.CC.

As mentioned above, if the high voltage generating circuit 70' as shown in FIG. 7 is provided on the chip 60, the terminal 69 can be omitted. However, when the high voltage generating circuit of FIG. 7 is coupled to a memory cell in which current flows in an operation mode, the voltage level at the source of the IGFET T.sub.73 drops. Therefore, the capability of supplying the high voltage level to the non-volatile memory element, for example, M.sub.31 of FIG. 3, is weakened. However, if the C-MOS memory cell as shown in FIG. 4 is used, the above-mentioned disadvantages can be avoided. In practice, the high voltage generating circuit of FIG. 7 is designed such that .DELTA.V.sub.DD in the clock signal cycle of FIG. 8 is smaller than the threshold voltage of the IGFETs T.sub.41 or T.sub.43.

Although N-channel type IGFETs are used in the embodiment in FIG. 3, P-channel type IGFETs can be also used in the same way. Moreover, in the above embodiments, the non-volatile memory element (M.sub.31, M.sub.41) is not necessarily limited to the element shown in FIG. 1. It goes without saying that any non-volatile memory element of the so-called electrically rewritable non-volatile type having a variable threshold voltage can be used.

Claims

1. A semiconductor memory device having a plurality of memory cells on a single semiconductor chip, each of said memory cells comprising; a bistable circuit coupled between a reference voltage source and a power supply terminal and having two output terminals, one of said two output terminals being coupled to a true digit line via a first transfer gate, and the other output terminal being coupled to a complementary digit line via a second transfer gate, means for selectively supplying a first voltage or a second voltage higher than said first voltage to said bistable circuit through said power supply terminal, a non-volatile memory transistor having a control electrode coupled to one of said two output terminals of said bistable circuit, and having one of a source and drain coupled to the other of said two output terminals of said bistable circuit, for selectively storing the contents of said bistable circuit, and switching means coupled to the other of said source and drain of said non-volatile memory transistor for applying a driving voltage thereto, and a power-on reset circuit provided on said semiconductor chip and generating a reset signal when power for driving the memory device is supplied to said semiconductor chip, said switching means being activated by said reset signal to apply a driving voltage at the other of said source and drain of said non-volatile memory transistor.

2. A semiconductor memory device as claimed in claim 1, in which said first voltage is applied to said bistable circuit through said power supply terminal when said bistable circuit acts as an ordinary random access memory cell, while said second voltage is applied to said bistable circuit through said power supply terminal when data in said bistable circuit is to be sheltered in said non-volatile memory transistor.

3. A semiconductor device, comprising; a power-on reset circuit generating a reset signal whenever driving power is supplied to the semiconductor device, and at least one memory element, said memory element comprising a flip-flop circuit and a non-volatile transistor having a control electrode and two contact portions which act as a source region and a drain region, respectively, said control electrode of said non-volatile transistor being coupled to one output of said flip-flop circuit, one of said two contact portions of said non-volatile transistor being coupled to the other output of said flip-flop circuit, the other of said two contact portions receiving a driving voltage when data stored in said non-volatile transistor is to be written into said flip-flop circuit, and a switching transistor receiving said driving voltage at one terminal and being connected at another terminal to said non-volatile transistor, and being turned on in response to said reset signal generated by said power-on reset circuit; and said flip-flop circuit receiving a control voltage which can activate said non-volatile transistor when data in said flip-flop is to be stored in said non-volatile transistor.

4. A semiconductor device as claimed in claim 3, wherein said flip-flop circuit comprises two inverters of a complementary type, an input of one inverter being coupled to an output of the other inverter and an input of said other inverter being coupled to an output of said one inverter.

5. A semiconductor memory device as claimed in claim 1, wherein said non-volatile memory transistor comprises a dual gate device having a floating gate having at least one portion arranged proximate a drain region, and a control gate disposed above said floating gate, said non-volatile memory transistor performing a writing operation to store the contents of said bistable circuit upon the application of said second voltage across said control gate and said drain region.

6. A semiconductor memory device as claimed in claim 1, wherein said bistable circuit comprises a flip-flop circuit constituted of a pair of cross connected inverters, each of said inverters comprising a series connected depletion type IGFET and an enhancement type IGFET.

7. A semiconductor memory device as claimed in claim 6, wherein said bistable circuit comprises a flip-flop circuit constituted of a pair of cross-coupled inverters, each of said converters comprising a series connected P-channel MOSFET and N-channel MOSFET.

8. A semiconductor memory device as claimed in claim 1, wherein said means for selectively supplying comprises a select circuit disposed on said chip for selecting between a source of said first voltage and a source of said second voltage, both of said sources being located externally of said chip.

9. A semiconductor memory device as claimed in claim 1 further comprising means for generating said second voltage located on said chip, said second voltage generating means comprising a terminal for receiving said first voltage, a pair of serially connected transistors respectively receiving true and complemented control signals, a charging circuit connected between said transistors, a further transistor coupled between a source of said first voltage and an output of said charging circuit and receiving said true control signal, and an output terminal connected to said bistable circuits of said memory cells.

10. A semiconductor memory device as claimed in claim 9, wherein said charging circuit comprises a plurality of serially connected IGFETs having interconnected gates and drains, and a charging capacitor coupled to each said gate.