Claims
- 1. A read out method of a semiconductor memory device comprising:latching data on a data bus into a page latch; and transferring the data latched in the page latch to a cell matrix for programming the data at a first mode, and to a read out circuit for reading out the data without programming the data latched in the data latch into the cell matrix at a second mode.
- 2. The read out method of the semiconductor memory device according to the claim 1, wherein the second mode comprises:a test mode to test whether or not an error occurs at a data transfer circuit group including the data bus, the page latch, and the read out circuit.
- 3. The read out method of the semiconductor memory device according to the claim 1, wherein the second mode comprises:a test mode for confirming whether or not an error occurs.
- 4. The read out method of the semiconductor memory device according to the claim 1, further comprising:correcting error of data read from the read out circuit.
- 5. A read out method of a semiconductor memory device comprising:latching data on a data bus and an inspection data generated by an inspection bits generating circuit into a page latch; and transferring the data and the inspection data latched in the page latch to a cell matrix at a first mode for programming the data and the inspection data, and to a read out circuit for reading out the data without programming the data and the inspection data into the cell matrix at a second mode.
- 6. The read out method of the semiconductor memory device according to the claim 5, wherein the second mode comprises:a test mode to test whether or not an error occurs at a data transfer circuit group including the data bus, the page latch, and the read out circuit.
- 7. The read out method of the semiconductor memory device according to the claim 5, wherein the second mode comprises:a test mode for confirming whether or not an error occurs.
- 8. The read out method of the semiconductor memory device according to the claim 5, further comprising:correcting error of data read from the read out circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2000-066954 |
Mar 2000 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a division of Ser. No. 10/270,673 Oct. 16, 2002 now U.S. Pat. No. 6,731,538 which is a continuation-in-part of U.S. application Ser. No. 09/794,076, filed Feb. 28, 2001 abandon, the entire contents of which are incorporated herein by reference.
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-066954, filed Mar. 10, 2000, the entire contents of which are incorporated herein by reference.
US Referenced Citations (15)
Foreign Referenced Citations (2)
Number |
Date |
Country |
2000-127950 |
May 2000 |
JP |
2000-149581 |
May 2000 |
JP |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09/794076 |
Feb 2001 |
US |
Child |
10/270673 |
|
US |