This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2008-215849, filed on Aug. 25, 2008, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, a method of manufacturing a semiconductor memory device and a method of writing data into a semiconductor memory device.
2. Description of the Related Art
A ferroelectric random access memory (hereinafter referred to as FeRAM) is known as one of nonvolatile semiconductor memory devices. A FeRAM includes a ferroelectric capacitor in its memory cell and is capable of holding data without power supply, with the use of remnant polarization of its ferroelectric capacitor.
In terms of a FeRAM, it is known that a hysteresis of remnant polarization of the ferroelectric capacitor shifts depending on a condition or environment under which the FeRAM is used. Such characteristic of a FeRAM causes phenomena such as static imprint and dynamic imprint. The static imprint is that: when the FeRAM with certain data written therein is left under high temperature, it becomes difficult to write, into the FeRAM, data of a polarity opposite to that of the written data. Meanwhile, the dynamic imprint is that: when the same data is repeatedly read out, a margin for reading out the data is reduced, which gradually makes it difficult and eventually impossible to read out the data from the FeRAM.
Generally, these imprint phenomena have been considered to reduce reliability of a FeRAM. However, a semiconductor memory device is proposed in which the static imprint phenomenon is rather positively used to cause a FeRAM to serve as a ROM (see page 5 and FIG. 7 of Japanese Patent Application Publication No. Hei 10-150157, for example).
The proposed semiconductor memory device is formed as a ROM in a way that a FeRAM has data written thereto firstly, and then receives application of heat and a pulse voltage of the same polarity as the written data to cause a ferroelectric capacitor to enter a static imprint state.
However, the ROM formed in this manner has a shift of the hysteresis toward the polarity of the written data, and thus has a small margin for reading out the data. Accordingly, the ROM has a problem of reduction in the number of data read times until data cannot be read out any more due to the occurrence of the dynamic imprint phenomenon and the static imprint phenomenon.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device including a ferroelectric random access memory serving as a ROM, the method comprising: writing data into the ferroelectric random access memory, the data having a polarity opposite to that of ROM data; performing bake processing for a predetermined time period; and writing the ROM data into the ferroelectric random access memory.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device including a ferroelectric random access memory partitioned into a ROM region and a RAM region, the method comprising: forming a circuit controlling the ROM region and the RAM region separately; writing data into the ROM region, the data having a polarity opposite to that of ROM data; performing bake processing for a predetermined time period; and writing the ROM data into the ROM region.
According to another aspect of the present invention, there is provided a method of writing data into a semiconductor memory device, the method comprising: a first step of writing data into a ferroelectric random access memory cell, the data having a polarity opposite to that of data to be actually written; a second step of performing bake processing on the ferroelectric random access memory cell; and a third step of writing into the ferroelectric random access memory cell the data to be actually written.
Embodiments of the present invention will be described hereinbelow referring to the drawings.
In this embodiment, a description is given of a method of writing ROM data into a FeRAM in a semiconductor memory device, when the FeRAM is used as a ROM.
With the start of the writing process, firstly, data is written into a FeRAM. The data written here has an opposite polarity in which “1”s and “0”s in ROM data to be actually written are reversed (Step S01).
Thereafter, the semiconductor memory device is subjected to bake processing for a predetermined time period to cause a static imprint phenomenon to appear in the FeRAM (Step S02).
Then, the actual ROM data is written into the FeRAM (Step S03), and this process flow is finished.
As described above, in the present embodiment, the data having a polarity opposite to that of the actual ROM data is once written into the FeRAM when the FeRAM is used as a ROM. Thereafter, the FeRAM is subjected to bake processing to cause the static imprint phenomenon to forcefully appear in the FeRAM. This shifts the hysteresis of the ferroelectric capacitor. Here, the hysteresis of the actual ROM data shifts toward a direction in which a data read-out margin is increased.
Here, with the bake processing, the hysteresis shifts to the left in
As a result, when “1” is written, as ROM data, into the ferroelectric capacitor having a hysteresis located at the position indicated by the solid line, a data read-out margin (difference between “1” level and “0” level) m1 at the time of reading out the data is more than a data read-out margin m0 in the hysteresis obtained before the bake processing.
Here, with the bake processing, the hysteresis shifts to the right in
As a result, when “0” is written, as ROM data, into the ferroelectric capacitor having a hysteresis located at the position indicated by the solid line, a data read-out margin m1 at the time of reading out the data is, as in the above case, more than a data read-out margin m0 in the hysteresis obtained before the bake processing.
Next, a description is given of a dynamic imprint phenomenon appeared in the FeRAM having ROM data written therein.
From the FeRAM having ROM data written therein, data of the same values is always read out. For this reason, the FeRAM normally undergoes a dynamic imprint phenomenon, as well as the static imprint phenomenon caused by leaving the FeRAM under high temperature. The dynamic imprint phenomenon causes the hysteresis of the ferroelectric capacitor to shift every time data is read out. Here, the dynamic imprint phenomenon causes the hysteresis to shift to an opposite direction from the direction in which the hysteresis shifts due to the bake processing performed after writing the opposite-polarity data.
In this case, the hysteresis shifts to the right in
In this case, the hysteresis shifts to the left in
As described above, the appearance of the dynamic imprint phenomenon reduces the data read-out margin of the FeRAM having ROM data written therein.
In the FeRAM having ROM data written according to a method of the present embodiment, however, the data read-out margin at the start of use is increased by the bake processing. Accordingly, even if the read-out margin starts reducing due to the dynamic imprint phenomenon, the FeRAM still has a sufficient data read-out margin and is readable a considerable number of times before the occurrence of a read-out error.
In other words, compared to the conventional device, the present embodiment makes it possible to enhance a data read-out margin in a FeRAM serving as a ROM to cope with the dynamic/static imprint phenomena.
In this embodiment, a description is given of an example of a semiconductor memory device provided with a FeRAM partitioned into a ROM region and a RAM region.
A semiconductor memory device 100 of the present embodiment includes a FeRAM 1 and an operation control circuit 2. The FeRAM 1 is partitioned into a ROM region 11 and a RAM region 12.
In the present embodiment, the manufacturing method described in Embodiment 1 is used to write ROM data into the ROM region 11. If any data has already been written into the RAM region 12 before writing ROM data into the ROM region 11, a static imprint phenomenon appears also in the RAM region 12 after the bake processing. This may reduce the data read-out margin in the RAM region 12 at the actual use.
To avoid this, the operation control circuit 2 controls the operation of the FeRAM 1 to activate the ROM region 11 and the RAM region 12 separately.
To write the ROM data, the operation control circuit 2 activates only the ROM region 11, and does not activate the RAM region 12. Thus no data is written into the RAM region 12. This prevents the static imprint phenomenon from appearing in the RAM region 12 even after the bake processing.
As a specific method of such activation,
The process flow of writing the ROM data according to the present embodiment is made by adding a step (Step S11) at the beginning of the process flow shown in
The following steps (Steps S01 to S03) are the same as the steps denoted with the same reference numerals in the flow of
As an alternative example, as shown in
According to the present embodiment, even in a FeRAM partitioned into a ROM region and a RAM region, a data read-out margin in the ROM region can be enhanced, without reduction in a data read-out margin in the RAM region, to cope with the dynamic imprint phenomenon.
Having described the embodiments of the invention referring to the accompanying drawings, it should be understood that the present invention is not limited to those precise embodiments and various changes and modifications thereof could be made by one skilled in the art without departing from the spirit or scope of the invention as defined in the appended claims.
Number | Date | Country | Kind |
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2008-215849 | Aug 2008 | JP | national |