Semiconductor memory device using pipelined-buffer programming and related method

Abstract

Disclosed is a semiconductor memory device which is operable a pipelined-buffer programming and includes a cell array including a plurality of memory cells, a write driver circuit divided into a plurality of write units, each write unit programming memory cells with a first data, a sense amplifier circuit divided into plurality of read units of the same number as the plurality of write units, each read unit sensing bit lines of the cell array during a program verify operation, a selection circuit for selecting one of the write units and one of the read units in response to a column address and a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:

FIG. 1 shows a block diagram of a conventional semiconductor memory device with pipelined-buffer programming;

FIG. 2 shows a schematic data flow of a semiconductor memory device illustrated in FIG. 1;

FIG. 3 shows a semiconductor memory device according to the disclosed methods and systems;

FIG. 4 shows a schematic data flow of the present semiconductor memory device; and

FIG. 5 is a graph for describing a program speed of a semiconductor memory device according to the disclosed methods and systems.

Claims

1. A semiconductor memory device comprising: a cell array having a plurality of memory cells;a write driver circuit divided into N write units of the same size, wherein each write unit is capable of programming the memory cells with first data and wherein N is an integer of 2 or more;a sense amplifier circuit divided into N read units of the same size, wherein each read unit is capable of sensing bit lines of the cell array during a program verify operation; anda selection circuit for selecting one of the write units and one of the read units in response to an input address.

2. The memory device of claim 1, wherein the selection circuit can select one of the write units and one of the read units in response to a column address.

3. The memory device of claim 1, further comprising a data input circuit for providing the first data to the selected write unit during a program operation and for receiving verifying data from the selected read unit during the program verify operation.

4. The memory device of claim 3, further comprising: a write buffer for storing program data bits, the write buffer having a data size larger than the first data;a bit scanning circuit for storing the program data bits from the write buffer and scanning valid program data bits; anda write driver latch for latching the scanned valid program data bits, the scanned valid program data bits being the first data.

5. The memory device of claim 1, wherein the data input circuit comprises: a write buffer for storing program data bits, the write buffer having a data size larger than the first data;a bit scanning circuit for storing the program data bits from the write buffer and scanning valid program data bits; anda write driver latch for latching the scanned valid program data bits, the scanned valid program data bits being the first data.

6. The memory device of claim 4, wherein the write buffer has the same I/O structure as the write unit.

7. The memory device of claim 4, wherein the bit scanning circuit includes scan latch for storing the data bits from the write buffer.

8. The memory device of claim 4, wherein the write driver latch saves the scanned data bits temporarily and provides the scanned data bits to the write unit.

9. The memory device of claim 3, wherein the cell array consists of a memory bank.

10. The memory device of claim 3, wherein the plurality of memory cells are NOR-type flash memory cells.

11. A semiconductor memory device comprising: a cell array having a plurality of memory cells;a column select unit capable of selecting bit lines of the cell array in response to a column address;a write driver circuit divided into a plurality of write units, each write unit programming memory cells with N-bit data during a programming cycle, wherein N is a positive integer; anda sense amplifier circuit divided by a plurality of read units, each of which senses memory cells with N-bit data during a program verify operation; anda selection circuit responsive to a column address, selecting one among the write units during a programming operation and one among the read units during a program verify operation.

12. The memory device of claim 11, further comprising a data input circuit supplying N bits of program data to the selected write unit during a program operation and receiving N bits of verify data from the selected read unit during the program verify operation.

13. The memory device of claim 12, wherein the data input circuit comprises: a write buffer for storing program data bits, the write buffer having a data size larger than N-bit data;a bit scanning unit for searching valid program bits among N-bit data received from the write buffer; anda write driver latch for latching the scanned valid program data bits.

14. The memory device of claim 13, wherein the bit scanning unit comprises scan latch for storing the N-bit data received form the write buffer.

15. The memory device of claim 13, wherein the data input circuit further comprises a control unit for controlling the bit scanning unit and write driver latch to operate simultaneously, wherein the control unit is capable of determining a pass/fail based on received verify data.

16. The memory device of claim 11, wherein the read unit senses the N selected bit lines and generates program verify data during the program verify operation.

17. The memory device of claim 11, wherein the selection circuit enables a write unit and a read unit which are coupled to the bit lines selected by the column select unit.

18. The memory device of claim 11, wherein the cell array consists of a memory bank.

19. The memory device of claim 11, wherein the plurality of memory cells are NOR-type flash memory cells.