Semiconductor memory device

Abstract

A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and a bit line, with a gate connected to a word line. A first amplifier amplifies an I/O line pair to a first voltage and a second voltage higher than the first voltage. A second amplifier amplifies a bit line pair to the first voltage and a third voltage higher than the second voltage. A switch element switches the connection relationship between the I/O line pair and the bit line pair among a connected state, a disconnected state and a transmission limited state in which the potential transmitted is limited.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of semiconductor memory devices of the embodiments of the present invention.

FIG. 2 is a block diagram of a memory cell.

FIG. 3 is a block diagram of a first amplifier in Embodiments 1, 2, 3 and 4 of the present invention.

FIG. 4 is a block diagram of a switch element in Embodiments 1, 4 and 5 of the present invention.

FIG. 5 is a block diagram of a second amplifier in the embodiments of the present invention.

FIG. 6 is a timing chart showing the operation in Embodiment 1 of the present invention.

FIG. 7 is a block diagram of a switch element in Embodiment 2 of the present invention.

FIG. 8 is a timing chart showing the operation in Embodiment 2 of the present invention.

FIG. 9 is a block diagram of a switch element in Embodiment 3 of the present invention.

FIG. 10 is a timing chart showing the operation in Embodiment 3 of the present invention.

FIG. 11 is a timing chart showing the operation in Embodiment 4 of the present invention.

FIG. 12 is a block diagram of a first amplifier in Embodiment 5 of the present invention.

FIG. 13 is a timing chart showing the operation in Embodiment 5 of the present invention.

FIG. 14 is a block diagram of a conventional semiconductor memory device.

FIG. 15 is a timing chart showing the operation of the conventional semiconductor memory device.

Claims

1. A semiconductor memory device comprising: a memory cell array composed of a plurality of memory cells arranged in a matrix, each of the memory cells including a capacitor having a plate electrode connected to a common cell plate and a storage electrode and a transistor provided between the storage electrode of the capacitor and a bit line, a gate of the transistor being connected to a word line;a first amplifier for amplifying potentials of an I/O line pair to a first voltage and a second voltage higher than the first voltage;a second amplifier for amplifying potentials of a bit line pair to the first voltage and a third voltage higher than the second voltage; anda switch element for switching a connection relationship between the I/O line pair and the bit line pair among a connected state in which the lines are electrically connected, a disconnected state in which the lines are electrically disconnected, and a transmission limited state in which the lines are electrically connected but the potential transmitted is limited,wherein the voltage of the cell plate is set at a voltage higher than the first voltage and lower than the third voltage.

2. The device of claim 1, wherein the switch element includes a PMOS transistor and an NMOS transistor connected in parallel, provided each between one of the I/O line pair and one of the bit line pair and between the other of the I/O line pair and the other of the bit line pair.

3. The device of claim 1, wherein the switch element includes two NMOS transistors connected in parallel, provided each between one of the I/O line pair and one of the bit line pair and between the other of the I/O line pair and the other of the bit line pair.

4. The device of claim 1, wherein the switch element includes an NMOS transistor provided each between one of the I/O line pair and one of the bit line pair and between the other of the I/O line pair and the other of the bit line pair, and switches among the connected state, the disconnected state and the transmission limited state according to the level of a gate voltage of the NMOS transistor.

5. The device of claim 1, wherein in read operation and write operation, the switch element switches from the disconnected state to the connected state, the first amplifier performs amplification,the switch element switches from the connected state to the transmission limited state, andthe second amplifier performs amplification.

6. The device of claim 1, wherein in read operation and write operation, the switch element switches from the disconnected state to the connected state, the switch element switches from the connected state to the transmission limited state,the first amplifier performs amplification, andthe second amplifier performs amplification.

7. The device of claim 1, wherein the first amplifier includes a cross-coupled CMOS amplifier, and the second amplifier includes a cross-coupled CMOS amplifier.

8. The device of claim 1, wherein the first amplifier includes a cross-coupled CMOS amplifier, and the second amplifier includes a cross-coupled PMOS amplifier.

9. The device of claim 1, wherein the first amplifier includes a cross-coupled NMOS amplifier, and the second amplifier includes a cross-coupled PMOS amplifier.

10. The device of claim 1, wherein transistors constituting the first amplifier and transistors constituting the second amplifier are different in gate oxide film thickness.

11. The device of claim 1, wherein transistors constituting the first amplifier and transistors constituting the second amplifier are different in source-drain breakdown voltage.

12. The device of claim 1, wherein the capacitor is a ferroelectric capacitor having a ferroelectric film provided as an insulating film.