SEMICONDUCTOR MEMORY DEVICE

Abstract

The semiconductor memory device according to the present invention is a semiconductor memory device configured of a non-volatile memory and a volatile memory which holds a part of the data held by the non-volatile memory, and includes: j first holding units, each of which holds an address of the data, in the non-volatile memory, which corresponds to the data held in the volatile memory; and j second holding units corresponding to the j first holding units, in which each of the second holding units holds the information indicating whether or not the address held by the corresponding first holding unit is valid.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the invention. In the Drawings:

FIG. 1 is a block diagram showing an outline configuration of a semiconductor memory device according to the present invention;

FIG. 2A is a timing chart indicating the operation of the semiconductor memory device when a read hit occurs;

FIG. 2B is a timing chart indicating the operation of the semiconductor memory device when a read miss-hit occurs;

FIG. 3A is a timing chart indicating the operation of the semiconductor memory device when a write hit occurs;

FIG. 3B is a timing chart indicating the operation of the semiconductor memory device when a write miss-hit occurs;

FIG. 4 is a diagram showing in detail the configuration of a data cache unit according to the first embodiment of the present invention;

FIG. 5 is a diagram showing the configuration of a data holding/comparing element;

FIG. 6 is a timing chart indicating the comparison operation performed by the semiconductor memory device;

FIG. 7 is a timing chart indicating the initialization operation performed by the semiconductor memory device;

FIG. 8 is a diagram showing in detail the configuration of the data cache unit according to the second embodiment of the present invention;

FIG. 9 is a diagram showing in detail the configuration of the data cache unit according to a variation of the second embodiment;

FIG. 10 is a diagram showing in detail the configuration of the data cache unit according to the variation of the second embodiment;

FIG. 11 is a diagram showing the configuration of the data holding/comparing element according to the third embodiment of the present invention;

FIG. 12A is a timing chart indicating the comparison operation performed by the data holding/comparing element shown in FIG. 11 according to the third embodiment;

FIG. 12B is a timing chart indicating the reading operation of the data holding/comparing element shown in FIG. 11; and

FIG. 12C is a timing chart indicating the write operation of the data holding/comparing unit shown in FIG. 11.

Claims

1. A semiconductor memory device including a non-volatile memory and a volatile memory which holds a part of data held in said non-volatile memory, said semiconductor memory device comprising: j (j≧1) first holding units, each being operable to hold an address of the data in the non-volatile memory which corresponds to the data held in the volatile memory; andj second holding units, each corresponding to each of said j first holding units and being operable to hold information indicating whether or not the address held by the corresponding first holding unit is valid.

2. The semiconductor memory device according to claim 1, wherein each of said second holding units is operable to hold information indicating that the address is invalid when said semiconductor memory device is initialized, and to hold information indicating that the address is valid in the case where an address is written in the corresponding first holding unit.

3. The semiconductor memory device according to claim 2, further comprising: j first comparing units, each corresponding to each of said first holding units and being operable to compare an externally-inputted address signal with held data held by the corresponding first holding unit, so as to judge whether or not the held data matches the address signal;j second comparing units, each corresponding to each of said second holding units and each of said first comparing units, and being operable to compare the information held by the corresponding second holding unit with the information indicating that the address is valid, so as to judge whether or not the information match with each other; andj judging units, each being operable to judge that the address matches the address signal in the case where a result of the comparison made by said first comparing unit indicates that the address signal matches the held data and a result of the comparison made by the corresponding second comparing unit indicates that the information match.

4. The semiconductor memory device according to claim 3, wherein: each of said first holding units includes m (m≧1) first holding elements, each element holding 1-bit data;each of said first comparing units includes m first comparing elements, each element comparing between pieces of 1-bit data;each one of said first holding elements is paired with each one of said first comparing elements so as to form a first holding and comparing element;each of said second holding units holds 1-bit data;each of said second comparing units is operable to compare between pieces of 1-bit data;each one of second holding units is paired with each one of said second comparing units so as to form a second holding and comparing element; andj×(m+1) first holding and comparing elements and second holding and comparing elements are placed in an array.

5. The semiconductor memory device according to claim 4, wherein said first holding and comparing element and said second holding and comparing element have a same configuration.

6. The semiconductor memory device according to claim 5, wherein said m comparing elements included in said first comparing unit and said second comparing unit corresponding to said first comparing unit are connected to a same wiring, andeach of said judging units is operable to judge whether or not the address matches the externally-inputted address signal, based on a signal level of the wiring.

7. The semiconductor memory device according to claim 6, wherein each of said first comparing elements includes:a first transistor in which the address is connected to a gate of said first transistor and the wiring is connected to a drain of said first transistor;a second transistor in which an inverting signal of the address is connected to a gate of said second transistor and the wiring is connected to a drain of said second transistor;a third transistor in which an inverting signal of the address signal is connected to a gate of said third transistor, a source of said first transistor is connected to a drain of said third transistor, and VSS is connected to a source of said third transistor; anda fourth transistor in which the address signal is connected to a gate of said fourth transistor, a source of said second transistor is connected to a drain of said fourth transistor, and VSS is connected to a source of said fourth transistor.

8. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is initialized when power of said device is turned on.

9. The semiconductor memory device according to claim 2, wherein said semiconductor memory device is initialized when at least one of the non-volatile memory, the volatile memory and said first holding unit is reset.

10. The semiconductor memory device according to claim 1, further comprising: a selecting unit operable to select at least one of said first holding unit and said second holding unit;an updating unit operable to update the address held by said first holding unit selected by said selecting unit, and information held by said second holding unit selected by said selecting unit; anda controlling unit operable to control, based on an externally-inputted address signal, the selection of said first holding unit and said second holding unit performed by said selecting unit.

11. The semiconductor memory device according to claim 10, wherein said controlling unit is operable to perform control so that said selecting unit separately selects said first holding unit and said second holding unit.

12. The semiconductor memory device according to claim 10, further comprising a reading unit operable to read the address held by said first holding unit and the information held by said second holding unit,wherein each of said first holding units and each of said second holding Units respectively include:a first data path which allows conduction when said updating unit updates the address and the information; anda second data path which allows conduction when said reading unit reads the address and the information.

13. The semiconductor memory device according to claim 1, further comprising a first comparing unit operable to compare the address and an externally-inputted address signal so as to judge whether or not the address matches the address signal,wherein said non-volatile memory includesa reading unit operable to read the data held by said non-volatile memory,the read operation performed by said reading unit includes a first sequence and a second sequence which follows the first sequence,the first sequence is started at the same time when said first comparing unit compares the address and the address signal, andthe second sequence is operated when a result of the comparison indicates that the address matches the address signal, and is not operated when a result of the comparison indicates that the address does not match the address signal.

14. The semiconductor memory device according to claim 13, wherein the non-volatile memory further includesa writing unit operable to write data into the non-volatile memory,the writing by said writing unit includes the first sequence and the second sequence which follows the first sequence,the first sequence is started at the same time when said first comparing unit compares the address and the address signal, andthe second sequence is operated without waiting for termination of the comparison.

15. The semiconductor memory device according to claim 13, wherein the first sequence is an operation of selecting a word line of the non-volatile memory, andthe second sequence is an operation of selecting a bit line of the non-volatile memory.

16. The semiconductor memory device according to claim 13, further comprising: an outputting unit which has a tri-state output to output read data which is read from the non-volatile memory; andan inputting unit operable to input, to the volatile memory, the data outputted by said outputting unit,wherein control on a timing at which an output state of said outputting unit shifts from a Hi-Z output to an output of the read data and control on a timing at which said inputting unit is started up are performed based on a same signal.

17. A reading method used in a semiconductor memory device including a non-volatile memory and a volatile memory which holds a part of data held in the non-volatile memory and an address corresponding to the data, said method comprising: comparing an externally-inputted address signal and the address so as to judge whether or not the address signal matches the address;starting reading the data held in the non-volatile memory at the same time when said comparing is performed; andreading the data held in the non-volatile memory in the case where a result of said comparing indicates that the address signal does not match the address, and not reading the data in the case where a result of said comparing indicates that the address signal matches the address.