Semiconductor memory device

Abstract

A programmable non-volatile semiconductor memory device having which a sufficient operational margin with miniaturized memory cells. The memory device includes select gates 3, arranged in a first region on a substrate 1, floating gates 6, arranged in a second region, neighboring to the first region, first diffusion regions 7, arranged in a third region neighboring to the second region, and control gates 11 arranged above the floating gates 6. It also includes a driving circuit 22 for controlling the voltages applied to the substrate 1, select gates 3, first diffusion areas 7 and the controlling gates 11. At the time of reprogramming, the driving circuit 22 controls the voltages for first control and second control. The first control sets a low threshold voltage state, inclusive of the depletion state, for the bits, connected to a selected one of the control gates 11. The second control sets a low threshold voltage state or a high threshold voltage state of a desired enhancement state from one bit to another.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial plan view schematically showing the configuration of a semiconductor memory device according to a first example of the present invention.

FIG. 2 is a partial cross-sectional view, taken along line X-X′ of FIG. 1, schematically showing the configuration of a semiconductor memory device according to the first example of the present invention.

FIG. 3 is a partial cross-sectional view for illustrating a first example of the operation from an initial state to an L′ state of the semiconductor memory device according to the first example of the present invention.

FIG. 4 is a partial cross-sectional view for illustrating a second example of the operation from an initial state to an L′ state of the semiconductor memory device according to the first example of the present invention.

FIG. 5 is a partial cross-sectional view for illustrating a first example of the operation from an L′ state to an H/L state of the semiconductor memory device according to the first example of the present invention.

FIG. 6 is a partial cross-sectional view for illustrating a second example of the operation from an L′ state to an H/L state of the semiconductor memory device according to the first example of the present invention.

FIG. 7 is a partial cross-sectional view for illustrating an operation of verification of the semiconductor memory device according to the first example of the present invention.

FIGS. 8A, 8B and 8C are graphs showing an H state, an L′ state and an L state of the threshold voltage distribution in the memory cells of the semiconductor memory device according to the first example of the present invention.

FIG. 9 is a partial plan view schematically showing the configuration of the semiconductor memory device according to a related art example 1.

FIG. 10 is a partial cross-sectional view, taken along line Y-Y′ of FIG. 9, schematically showing the configuration of the semiconductor memory device according to the related art example 1.

FIG. 11 is a partial plan view schematically showing the configuration of the select gate in an erase block of the semiconductor memory device according to the related art example 1.

FIG. 12 is a partial cross-sectional view for illustrating the readout operation of the semiconductor memory device according to the related art example 1, analyzed by the present invention.

FIG. 13 is a partial cross-sectional view for illustrating a programming operation of the semiconductor memory device according to the related art example 1, analyzed by the present invention.

FIG. 14 is a partial cross-sectional view for illustrating a first erase operation of the semiconductor memory device according to the related art example 1, analyzed by the present invention.

FIG. 15 is a partial cross-sectional view for illustrating a second erase operation of the semiconductor memory device according to the related art example 1, analyzed by the present invention.

FIGS. 16A, 16B and 16C are graphs showing an H state, a depletion state and an L state of the threshold voltage distribution in a memory cell of the semiconductor memory device according to the related art example 1, analyzed by the present invention.

Claims

1. A semiconductor memory device comprising: a plurality of storage nodes provided on a substrate;a plurality of control gates arranged above said storage nodes; anda driving circuit that controls voltages applied to said substrate and said control gates;said driving circuit exercising a first control and a second control, by controlling said voltages, at the time of rewriting operation; said first control setting a low threshold voltage state, inclusive of a depletion state, for bits, connected to a selected one of said control gates; said second control setting a low threshold voltage state or a high threshold voltage state of a desired enhancement state, per said bit.

2. The semiconductor memory device according to claim 1, further comprising: a plurality of select gates, each arranged in a second region adjacent to a first region where said storage nodes are arranged;said driving circuit controlling the voltages applied to said select gates.

3. The semiconductor memory device according to claim 1, further comprising: a plurality of local bit lines, each arranged in a third region adjacent to said first region where said storage nodes are arranged;said driving circuit controlling the voltage applied to said local bit line or lines.

4. The semiconductor memory device according to claim 2, further comprising: a plurality of local bit lines, each arranged in a third region adjacent to said first region where said storage nodes are arranged;said driving circuit controlling the voltage applied to said local bit line or lines.

5. The semiconductor memory device according to claim 1 wherein said driving circuit applies a negative voltage and a positive voltage to said control gate and to said substrate, respectively, at the time of said first control, to draw electrons from said storage node or nodes to said substrate.

6. The semiconductor memory device according to claim 2 wherein said driving circuit applies a negative voltage and a positive voltage to said control gate and to said substrate, respectively, at the time of said first control, to draw electrons from said storage node or nodes to said substrate.

7. The semiconductor memory device according to claim 3 wherein said driving circuit applies a negative voltage and a positive voltage to said control gate and to said substrate, respectively, at the time of said first control, to draw electrons from said storage node or nodes to said substrate.

8. The semiconductor memory device according to claim 2 wherein said driving circuit applies a negative voltage and a positive voltage to said control gate and to said select gate, respectively, at the time of said first control, to draw electrons from said storage node or nodes to said select gate or gates.

9. The semiconductor memory device according to claim 3 wherein said driving circuit applies a negative voltage and a positive voltage to said control gate and to said select gate, respectively, at the time of said first control, to draw electrons from said storage node or nodes to said select gate or gates.

10. The semiconductor memory device according to claim 5 wherein said driving circuit controls the voltages, at the time of said second control, to inject electrons selectively into said storage node or nodes.

11. The semiconductor memory device according to claim 8 wherein said driving circuit controls the voltages, at the time of said second control, to inject electrons selectively into said storage node or nodes.

12. The semiconductor memory device according to claim 10 wherein said driving circuit applies the voltages as pulsed voltages two or more times, at the time of said second control, to carry out verification of said storage node or nodes for matching to a desired threshold voltage.

13. The semiconductor memory device according to claim 11 wherein said driving circuit applies the voltages as pulsed voltages two or more times, at the time of said second control, to carry out verification of said storage node or nodes for matching to a desired threshold voltage.

14. The semiconductor memory device according to claim 1 wherein said driving circuit performs said first control for one of said control gates in a predetermined block and subsequently performs said second control for said one control gate.

15. The semiconductor memory device according to claim 2 wherein said driving circuit performs said first control for one of said control gates in a predetermined block and subsequently performs said second control for said one control gate.

16. The semiconductor memory device according to claim 3 wherein said driving circuit performs said first control for one of said control gates in a predetermined block and subsequently performs said second control for said one control gate.

17. The semiconductor memory device according to claim 1 wherein said driving circuit performs said first control for all of said control gates in a predetermined block and subsequently performs said second control for an optional one of said control gates.

18. The semiconductor memory device according to claim 2 wherein said driving circuit performs said first control for all of said control gates in a predetermined block and subsequently performs said second control for an optional one of said control gates.

19. The semiconductor memory device according to claim 3 wherein said driving circuit performs said first control for all of said control gates in a predetermined block and subsequently performs said second control for an optional one of said control gates.

20. The semiconductor memory device according to claim 14 wherein said driving circuit performs said first control for all of said control gates in a predetermined block and subsequently performs said second control for an optional one of said control gates.